NeuroNAS: Enhancing Efficiency of Neuromorphic In-Memory Computing for Intelligent Mobile Agents through Hardware-Aware Spiking Neural Architecture Search

TL;DR

The paper addresses the challenge of designing energy-efficient neuromorphic SNNs for intelligent mobile agents under tight hardware constraints. It introduces NeuroNAS, a hardware-aware spiking NAS framework that optimizes SNN operations, constructs neural-cell based architectures, and evaluates candidates with a quantization-aware fitness function within IMC hardware budgets. NeuroNAS achieves up to 92% area savings, 1.2x latency improvements, 84% energy reductions, and up to 6.6x search-time speed-ups across CIFAR-10, CIFAR-100, and TinyImageNet-200, outperforming state-of-the-art methods that fail to satisfy constraints simultaneously. The approach enables rapid, automatic design of energy-efficient neuromorphic IMC solutions for mobile agents, bridging the gap between NAS, SNNs, and hardware-aware deployment.

Abstract

Intelligent mobile agents (e.g., UGVs and UAVs) typically demand low power/energy consumption when solving their machine learning (ML)-based tasks, since they are usually powered by portable batteries with limited capacity. A potential solution is employing neuromorphic computing with Spiking Neural Networks (SNNs), which leverages event-based computation to enable ultra-low power/energy ML algorithms. To maximize the performance efficiency of SNN inference, the In-Memory Computing (IMC)-based hardware accelerators with emerging device technologies (e.g., RRAM) can be employed. However, SNN models are typically developed without considering constraints from the application and the underlying IMC hardware, thereby hindering SNNs from reaching their full potential in performance and efficiency. To address this, we propose NeuroNAS, a novel framework for developing energyefficient neuromorphic IMC for intelligent mobile agents using hardware-aware spiking neural architecture search (NAS), i.e., by quickly finding an SNN architecture that offers high accuracy under the given constraints (e.g., memory, area, latency, and energy consumption). Its key steps include: optimizing SNN operations to enable efficient NAS, employing quantization to minimize the memory footprint, developing an SNN architecture that facilitates an effective learning, and devising a systematic hardware-aware search algorithm to meet the constraints. Compared to the state-of-the-art techniques, NeuroNAS quickly finds SNN architectures (with 8bit weight precision) that maintain high accuracy by up to 6.6x search time speed-ups, while achieving up to 92% area savings, 1.2x latency improvements, 84% energy savings across different datasets (i.e., CIFAR-10, CIFAR-100, and TinyImageNet-200); while the state-of-the-art fail to meet all constraints at once.

Figures (14)

• Figure 1: (a) Intelligent mobile agents are typically expected to provide high accuracy with low power/energy processing to solve ML-based tasks. (b) Breakdown of SNN inference energy on von-Neumann-based neuromorphic accelerators: PEASE Ref_Roy_PEASE_ISLPED17, TrueNorth Ref_Akopyan_TrueNorth_TCAD15, and SNNAP Ref_Sen_ApproxSNN_DATE17; adapted from Ref_Krithivasan_SpikeBundle_ISLPED19. (c) Accuracy vs. memory of different SNNs on CIFAR-10 dataset: CIFARNet1 Ref_Wu_DirectTrainSNNs_AAAI19, CIFARNet2 Ref_Fang_MemTConstantSNNs_ICCV21, ResNet11 Ref_Lee_SpikeBackprop_FNINS20, ResNet19 Ref_Zheng_LargerSNNs_AAAI21, AutoSNN Ref_Na_AutoSNN_ICML22, and SpikeNAS Ref_Putra_SpikeNAS_arXiv24; data are obtained from studies in Ref_Na_AutoSNN_ICML22Ref_Putra_SpikeNAS_arXiv24. (d) Energy efficiency of different types of single-core SNN accelerators: CMOS-based fully digital design, CMOS-based mixed-signal design, and RRAM-based IMC design; based on data from Ref_Basu_SNNicSurvey_CICC22.
• Figure 2: Results from the case study considering the CIFAR-100 dataset: (a) number of weight parameters and accuracy; and (b) area, latency, and energy consumption when running SNNs on an RRAM-based IMC hardware Ref_Moitra_SpikeSim_TCAD23.
• Figure 3: Overview of our novel contributions in the NeuroNAS framework.
• Figure 4: SNN macro-architecture with 2 neural cells, and each cell is a DAG whose edge denotes a specific pre-defined operation; adapted from Ref_Kim_SNASNet_ECCV22.
• Figure 5: The SNN IMC hardware architecture that is considered in this work. It is based on the SpikeFlow architecture Ref_Moitra_SpikeSim_TCAD23.