Logo
ScienceStack
Table of Contents
Fetching ...
Sign In

An Open-Source Fast Parallel Routing Approach for Commercial FPGAs

Xinshi Zang, Wenhao Lin, Shiju Lin, Jinwei Liu, Evangeline F. Y. Young

TL;DR

The paper tackles the time-intensive routing stage in commercial FPGA flows by introducing an open-source parallel routing framework that combines a Recursive Partitioning Ternary Tree (RPTT) for multi-net parallelism with a Hybrid Updating Strategy (HUS) to accelerate congestion resolution. Built on the PathFinder-style negotiation routing, the method operates on theRouting Resource Graph of UltraScale+ FPGAs and uses a connection-based routing approach to maximize parallelism. Experimental results on FPGA24 benchmarks show the approach achieves roughly a twofold speedup over RWRoute and delivers up to a 31% reduction in critical-path wirelength compared to Vivado, with ablations confirming the benefits of RPTT and HUS and analysis of thread counts guiding parallelization. Overall, the work demonstrates practical, open-source gains in both runtime and routing quality for commercial FPGA devices, with meaningful implications for faster compilation and improved timing.

Abstract

In the face of escalating complexity and size of contemporary FPGAs and circuits, routing emerges as a pivotal and time-intensive phase in FPGA compilation flows. In response to this challenge, we present an open-source parallel routing methodology designed to expedite routing procedures for commercial FPGAs. Our approach introduces a novel recursive partitioning ternary tree to augment the parallelism of multi-net routing. Additionally, we propose a hybrid updating strategy for congestion coefficients within the routing cost function to accelerate congestion resolution in negotiation-based routing algorithms. Evaluation on public benchmarks from the FPGA24 routing contest demonstrates the efficacy of our parallel router. It achieves a 2x speedup compared to the academic serial router RWRoute. Furthermore, when compared to the industry-standard tool Vivado, our approach not only delivers a 2x acceleration but also yields a notable 31% enhancement in critical-path wirelength.

An Open-Source Fast Parallel Routing Approach for Commercial FPGAs

TL;DR

The paper tackles the time-intensive routing stage in commercial FPGA flows by introducing an open-source parallel routing framework that combines a Recursive Partitioning Ternary Tree (RPTT) for multi-net parallelism with a Hybrid Updating Strategy (HUS) to accelerate congestion resolution. Built on the PathFinder-style negotiation routing, the method operates on theRouting Resource Graph of UltraScale+ FPGAs and uses a connection-based routing approach to maximize parallelism. Experimental results on FPGA24 benchmarks show the approach achieves roughly a twofold speedup over RWRoute and delivers up to a 31% reduction in critical-path wirelength compared to Vivado, with ablations confirming the benefits of RPTT and HUS and analysis of thread counts guiding parallelization. Overall, the work demonstrates practical, open-source gains in both runtime and routing quality for commercial FPGA devices, with meaningful implications for faster compilation and improved timing.

Abstract

In the face of escalating complexity and size of contemporary FPGAs and circuits, routing emerges as a pivotal and time-intensive phase in FPGA compilation flows. In response to this challenge, we present an open-source parallel routing methodology designed to expedite routing procedures for commercial FPGAs. Our approach introduces a novel recursive partitioning ternary tree to augment the parallelism of multi-net routing. Additionally, we propose a hybrid updating strategy for congestion coefficients within the routing cost function to accelerate congestion resolution in negotiation-based routing algorithms. Evaluation on public benchmarks from the FPGA24 routing contest demonstrates the efficacy of our parallel router. It achieves a 2x speedup compared to the academic serial router RWRoute. Furthermore, when compared to the industry-standard tool Vivado, our approach not only delivers a 2x acceleration but also yields a notable 31% enhancement in critical-path wirelength.
Paper Structure (14 sections, 4 equations, 7 figures, 3 tables, 2 algorithms)

This paper contains 14 sections, 4 equations, 7 figures, 3 tables, 2 algorithms.

Table of Contents

  1. Introduction
  2. Preliminaries
  3. Ultrascale+ FPGA Architecture
  4. Routing Resource Graph
  5. FPGA routing algorithm
  6. Methodology
  7. Recursive Partitioning Ternary Tree (RPTT)
  8. Hybrid Updating Strategy (HUS)
  9. Experimental Results
  10. Benchmarks
  11. Overall Performance
  12. Ablation Studies
  13. Impact of The Number of Threads
  14. Conclusion

Figures (7)

  • Figure 1: UltraScale+ FPGA with columnar resources
  • Figure 2: Construction of a routing resource graph
  • Figure 3: The framework of our parallel router
  • Figure 4: Ten connections with one cutline
  • Figure 5: RPTT for the connections in Fig. 4
  • ...and 2 more figures