SubLock: Sub-Circuit Replacement based Input Dependent Key-based Logic Locking for Robust IP Protection

TL;DR

A novel input dependent key-based logic locking (IDKLL) that effectively prevents SAT-based attacks with low overhead and a sub-circuit replacement based IDKLL approach called SubLock that locks the design by replacing the original sub-circuits with the corresponding IDKLL based locked circuit to prevent SAT attack with low overhead.

Abstract

Intellectual Property (IP) piracy, overbuilding, reverse engineering, and hardware Trojan are serious security concerns during integrated circuit (IC) development. Logic locking has proven to be a solid defence for mitigating these threats. The existing logic locking techniques are vulnerable to SAT-based attacks. However, several SAT-resistant logic locking methods are reported; they require significant overhead. This paper proposes a novel input dependent key-based logic locking (IDKLL) that effectively prevents SAT-based attacks with low overhead. We first introduce a novel idea of IDKLL, where a design is locked such that it functions correctly for all input patterns only when their corresponding valid key sequences are applied. In contrast to conventional logic locking, the proposed IDKLL method uses multiple key sequences (instead of a single key sequence) as a valid key that provides correct functionality for all inputs. Further, we propose a sub-circuit replacement based IDKLL approach called SubLock that locks the design by replacing the original sub-circuitry with the corresponding IDKLL based locked circuit to prevent SAT attack with low overhead. The experimental evaluation on ISCAS benchmarks shows that the proposed SubLock mitigates the SAT attack with high security and reduced overhead over the well-known existing methods.

Figures (12)

• Figure 1: Logic Locking in IC development. Applying logic locking for mitigating various threats (i.e., IP Piracy, Overbuilding, Hardware Trojan and Reverse Engineering) during the IC life cycle.
• Figure 2: Locking a half adder circuit using input dependent key-based logic locking. The locked circuit provides correct output for the input patterns $\{"00", "01"\}$ and $\{"10", '11"\}$ only when the two key sequences $K_1 K_2 = "01"$ and $"10"$ are applied respectively as a valid key.
• Figure 3: An example of input dependent key-based logic locking, where the output bits are kept don't cares (x) for all the remaining incorrect key values, $i.e.$ "00" and "11". The locked circuit provides correct output for the sets of input patterns {"000", "001", "010", "011"} and {"100", "101", "110", "111"} only when "01" and "10" key sequences are applied respectively.
• Figure 4: The structure of LUT based memory for extracting the correct key sequence for the locked circuit shown as in (a) Figure \ref{['fig2']} (b) Figure \ref{['fig1']} (c) Optimized structure of LUT based memory.
• Figure 5: Example for integrating LUT based tamper-proof memory with the locked circuit to achieve correct functionality.