Designing Unit Ising Models for Logic Gate Simulation through Integer Linear Programming

TL;DR

This work targets efficient representation of Boolean logic as Ising Hamiltonians with unit coefficients to improve robustness against flux noise in quantum annealers. It proposes an integer linear programming framework to design zero-input unit Ising models for basic gates and to assemble them into combinational circuits that support forward and backward (inverse) computation. A concrete factorization case study demonstrates a HUBO-to-QUBO pathway yielding area-optimal $O(n^2)$ models, and the authors introduce Application-Specific Unit Quantum Annealers (ASUQAs) as ASIC-like hardware for targeted one-way functions. The results highlight practical implications for factoring RSA-like problems with specialized quantum hardware and contrast unit Ising designs with typical minor-embedding requirements on GPQAs.

Abstract

An Ising model is defined by a quadratic objective function known as the Hamiltonian, composed of spin variables that can take values of either $-1$ or $+1$. The goal is to assign spin values to these variables in a way that minimizes the value of the Hamiltonian. Ising models are instrumental in tackling many combinatorial optimization problems, leading to significant research in developing solvers for them. Notably, D-Wave Systems has pioneered the creation of quantum annealers, programmable solvers based on quantum mechanics, for these models. This paper introduces unit Ising models, where all non-zero coefficients of linear and quadratic terms are either $-1$ or $+1$. Due to the limited resolution of quantum annealers, unit Ising models are more suitable for quantum annealers to find optimal solutions. We propose a novel design methodology for unit Ising models to simulate logic circuits computing Boolean functions through integer linear programming. By optimizing these Ising models with quantum annealers, we can compute Boolean functions and their inverses. With a fixed unit Ising model for a logic circuit, we can potentially design Application-Specific Unit Quantum Annealers (ASUQAs) for computing the inverse function, which is analogous to Application-Specific Integrated Circuits (ASICs) in digital circuitry. For instance, if we apply this technique to a multiplication circuit, we can design an ASUQA for factorization of two numbers. Our findings suggest a powerful new method for compromising the RSA cryptosystem by leveraging ASUQAs in factorization.

Figures (9)

• Figure 1: Illustrating an Ising model with five spin variables as a weighted graph and its minor-embedding into a $3\times 2$-qubit cell quantum annealer.
• Figure 2: Illustrating a minor embedding of an Ising model with $K_{13}$ topology into the Chimera graph topology with $3\times 3$$K_{4,4}$'s
• Figure 3: An Ising model $H_{\rm AND}(a,b,x)$, a unit Ising model $H^{u}_{\rm AND}(a,b,x,u)$ and a zero-input unit Ising model $H^{zu}_{\rm AND}(a,b,x,u)$ for simulating the AND gate
• Figure 4: A logic circuit with inputs $a, b, c$ and outputs $x,y,z$ and the unit Ising model simulating it.
• Figure 5: Illustrating zero-input unit Ising models $H^{zu}_{OR}(a,b,x,u)$ and $H^{zu}_{OR}(\overline{a},b,x,u)$