Unified Architecture for Quantum Lookup Tables

TL;DR

This work tackles the challenge of efficient quantum access to classical data via lookup-table oracles (QRAM) and the high resource costs of fault-tolerant implementations. It introduces a unified, parameterized architecture that subsumes prior QRAM designs and supports planar 2D connectivity while enabling sublinear scaling in qubits, T gates, and error, through a general three-stage data-lookup framework. The framework, along with planar layouts and entanglement-distillation techniques, yields novel regimes such as simultaneous sublinear scaling and log-scaling infidelity, offering hardware-aware tradeoffs for memory size and word size. Collectively, the results provide a comprehensive blueprint for resilient, resource-efficient quantum data lookup suitable for integrating into end-to-end quantum algorithms on near- and far-term devices.

Abstract

Quantum access to arbitrary classical data encoded in unitary black-box oracles underlies interesting data-intensive quantum algorithms, such as machine learning or electronic structure simulation. The feasibility of these applications depends crucially on gate-efficient implementations of these oracles, which are commonly some reversible versions of the boolean circuit for a classical lookup table. We present a general parameterized architecture for quantum circuits implementing a lookup table that encompasses all prior work in realizing a continuum of optimal tradeoffs between qubits, non-Clifford gates, and error resilience, up to logarithmic factors. Our architecture assumes only local 2D connectivity, yet recovers results that previously required all-to-all connectivity, particularly, with the appropriate parameters, poly-logarithmic error scaling. We also identify novel regimes, such as simultaneous sublinear scaling in all parameters. These results enable tailoring implementations of the commonly used lookup table primitive to any given quantum device with constrained resources.

Figures (20)

• Figure 1: A high-level description of a quantum router, the router status is set to $\ket{a}$. Incident qubit $\ket{b}$ will be routed to the left (right) when the router state is set to $\ket{0}$ ($\ket{1}$).
• Figure 2: High-level routing scheme for the fan-out architecture. The address bits $\ket{010}$ are entangled with their corresponding routers at each level. In the end the stored classical data at memory location $x_2$ is queried.
• Figure 3: (a) A single CSWAP router that takes input qubit and sends it to one of its child nodes based on its state. (b) It takes four qubits to maintain a CSWAP router. The $in_j$ register takes in input and directs the input qubit to either the left or right register depending on the state of $t_j$.
• Figure 4: High-level routing scheme for the bucket-brigade architecture. The address bits $\ket{010}$ are sent in from the root level router to set all the routers in the corresponding query path to the correct state. The routers not in the query path remain inactive.
• Figure 5: (a) The linear routers $\mathbf{L}_0$ and $\mathbf{L}_1$ are configured based on the value of address bits which are set to $\ket{00}$. For two address bits, four rounds of multi-controlled CNOT gates are applied to handle all possible addresses that can occur in superposition, with $q_i$ as the target and the status of $\mathbf{L}_0$ and $\mathbf{L}_1$ as the controls. (b) For round $i=0$, the multi-control CNOT is shown. The value of control qubit $q$ is set to $1$, since $i=\ket{00}$. (c) For round $i=3$, the value of control qubit $q$ is set to $0$. This holds for any round $i\neq \ket{00}$.

Theorems & Definitions (21)

• Theorem 1.1: Informal version of Theorem \ref{['thm: unconditional_optimal']} and Corollary \ref{['cor: uncond_opt']}
• Theorem 1.2: Informal version of Theorem \ref{['thm: unconditional_optimal_branch_b_first']} and Theorem \ref{['thm: sequential_readout']}
• Theorem 3.1
• Corollary 3.2
• proof
• Lemma 4.1
• proof
• Lemma 4.2
• Corollary 4.3
• Theorem 4.4