Design, Implementation and Evaluation of the SVNAPOT Extension on a RISC-V Processor

TL;DR

This work tackles MMU overhead under memory pressure in RISC-V by extending SVNAPOT to collocate $4\text{KB}$ and $64\text{KB}$ pages within a single L2 TLB structure using VPN partitioning. The authors implement per-entry N bits, adapt Insert/Lookup/Flush, and validate with a Linux kernel and a Rocket core, complemented by FireSim-based FPGA simulations. Results show up to a $16\times$ reduction in PTWs and a $4\text{MB}$ L2 reach improvement, with hashjoin achieving a $4.2\%$ speedup and a $14.2\%$ drop in L2 misses, while maintaining modest area overhead. These findings suggest SVNAPOT can meaningfully reduce memory-management overhead on RISC-V and highlight avenues for alternative TLB organizations, contiguity-driven OS support, and OS-transparent large-page mechanisms.

Abstract

The RISC-V SVNAPOT Extension aims to remedy the performance overhead of the Memory Management Unit (MMU), under heavy memory loads. The Privileged Specification defines additional Natural-Power-of-Two (NAPOT) multiples of the 4KB base page size, with 64KB as the default candidate. In this paper we extend the MMU of the Rocket Chip Generator, in order to manage the collocation of 64KB pages along with 4KB pages in the L2 TLB. We present the design challenges we had to overcome and the trade-offs of our design choices. We conduct a preliminary sensitivity analysis of the L2 TLB with different configurations/page sizes. Finally, we summarize on techniques which could further improve memory management performance on RISC-V systems.

Figures (2)

• Figure 1: VPN Partitioning
• Figure 2: Experimental Results. The x axis in all diagrams reports Memory Size (KB) in log2 scale.