Design and Implementation of a Low-Power Low-Noise Biopotential Amplifier in 28 nm CMOS Technology with a Compact Die-Area of 2500 $μ$m$^2$

TL;DR

This paper presents a compact low-power, low-noise bioamplifier for multi-channel electrode arrays, aimed at recording action potentials, which achieves a notable decrease in both size and power consumption.

Abstract

This paper presents a compact low-power, low-noise bioamplifier for multi-channel electrode arrays, aimed at recording action potentials. The design we put forth attains a notable decrease in both size and power consumption. This is achieved by incorporating an active lowpass filter that doesn't rely on bulky DC-blocking capacitors, and by utilizing the TSMC 28 nm HPC CMOS technology. This paper presents extensive simulation results of noise and results from measured performance. With a mid-band gain of 58 dB, a -3 dB bandwidth of 7 kHz (from 150 Hz to 7.1 kHz), and an input-referred noise of 15.8 $μ$V$_{\rm rms}$ corresponding to a NEF of 12. The implemented design achieves a favourable trade-off between noise, area, and power consumption, surpassing previous findings in terms of size and power. The amplifier occupies the smallest area of 2500 $μ$m$^2$ and consumes only 3.4 $μ$W from a 1.2 V power supply corresponding to a power efficiency factor of 175 and an area efficiency factor of 0.43, respectively.

Figures (16)

• Figure 1: Block diagram of an implanted neural recording system comprising of acquisition, interface readout, and transmission stages lemaire2022preliminary.
• Figure 2: Frequency response of high-Pass filter implementation using low-pass filter in feedback.
• Figure 3: Proposed LNA systemic schema with high-Pass filter implemented through low-pass filter feedback.
• Figure 4: Circuit diagrams of (a) $OTA_1$, (b) $OTA_2$, (c) $R_{eq}$.
• Figure 5: Test PCB of the LNA.