RISC-V processor enhanced with a dynamic micro-decoder unit

TL;DR

A micro-decoding unit inspired by CISC processors into a RISC-V core should provide flexibility to RISC-V processor architectures and enable dynamic custom instruction sequences execution whose usage could be, for instance to compress binaries, obfuscate behavior, etc.

Abstract

For years, the open-source RISC-V instruction set has been driving innovation in processor design, spanning from high-end cores to low-cost or low-power cores. After a decade of evolution, RISC architectures are now as mature as the CISC architectures popularized by industry giant Intel. Security and energy efficiency are now joining execution speed among the design constraints. In this article, we assess the benefits and costs associated with integrating a micro-decoding unit inspired by CISC processors into a RISC-V core. This unit, added in a specific pipeline stage, should enable dynamic custom instruction sequences execution whose usage could be, for instance to compress binaries, obfuscate behavior, etc.

Figures (2)

• Figure 1: CV64A6 core architecture enhanced with our micro-decoding unit
• Figure 2: Micro-decoding unit ROM content for macro-instruction encoding for S-Box computation