Logo
ScienceStack
Table of Contents
Fetching ...
Sign In

Enhancing Dropout-based Bayesian Neural Networks with Multi-Exit on FPGA

Hao Mark Chen, Liam Castelli, Martin Ferianc, Hongyu Zhou, Shuanglong Liu, Wayne Luk, Hongxiang Fan

TL;DR

An algorithm and hardware co-design framework that can generate field-programmable gate array (FPGA)-based accelerators for efficient BayesNNs and a transformation framework that can generate FPGA-based accelerators for the proposed efficient multi-exit BayesNNs are introduced.

Abstract

Reliable uncertainty estimation plays a crucial role in various safety-critical applications such as medical diagnosis and autonomous driving. In recent years, Bayesian neural networks (BayesNNs) have gained substantial research and industrial interests due to their capability to make accurate predictions with reliable uncertainty estimation. However, the algorithmic complexity and the resulting hardware performance of BayesNNs hinder their adoption in real-life applications. To bridge this gap, this paper proposes an algorithm and hardware co-design framework that can generate field-programmable gate array (FPGA)-based accelerators for efficient BayesNNs. At the algorithm level, we propose novel multi-exit dropout-based BayesNNs with reduced computational and memory overheads while achieving high accuracy and quality of uncertainty estimation. At the hardware level, this paper introduces a transformation framework that can generate FPGA-based accelerators for the proposed efficient multi-exit BayesNNs. Several optimization techniques such as the mix of spatial and temporal mappings are introduced to reduce resource consumption and improve the overall hardware performance. Comprehensive experiments demonstrate that our approach can achieve higher energy efficiency compared to CPU, GPU, and other state-of-the-art hardware implementations. To support the future development of this research, we have open-sourced our code at: https://github.com/os-hxfan/MCME_FPGA_Acc.git

Enhancing Dropout-based Bayesian Neural Networks with Multi-Exit on FPGA

TL;DR

An algorithm and hardware co-design framework that can generate field-programmable gate array (FPGA)-based accelerators for efficient BayesNNs and a transformation framework that can generate FPGA-based accelerators for the proposed efficient multi-exit BayesNNs are introduced.

Abstract

Reliable uncertainty estimation plays a crucial role in various safety-critical applications such as medical diagnosis and autonomous driving. In recent years, Bayesian neural networks (BayesNNs) have gained substantial research and industrial interests due to their capability to make accurate predictions with reliable uncertainty estimation. However, the algorithmic complexity and the resulting hardware performance of BayesNNs hinder their adoption in real-life applications. To bridge this gap, this paper proposes an algorithm and hardware co-design framework that can generate field-programmable gate array (FPGA)-based accelerators for efficient BayesNNs. At the algorithm level, we propose novel multi-exit dropout-based BayesNNs with reduced computational and memory overheads while achieving high accuracy and quality of uncertainty estimation. At the hardware level, this paper introduces a transformation framework that can generate FPGA-based accelerators for the proposed efficient multi-exit BayesNNs. Several optimization techniques such as the mix of spatial and temporal mappings are introduced to reduce resource consumption and improve the overall hardware performance. Comprehensive experiments demonstrate that our approach can achieve higher energy efficiency compared to CPU, GPU, and other state-of-the-art hardware implementations. To support the future development of this research, we have open-sourced our code at: https://github.com/os-hxfan/MCME_FPGA_Acc.git
Paper Structure (26 sections, 3 equations, 6 figures, 3 tables, 2 algorithms)

This paper contains 26 sections, 3 equations, 6 figures, 3 tables, 2 algorithms.

Table of Contents

  1. Introduction
  2. Background and Related Work
  3. Bayesian Neural Networks
  4. Dropout-based Approximations for BayesNNs
  5. MCD-based BayesNNs
  6. Masksembles
  7. Multi-Exit DNNs
  8. Related Work
  9. Multi-Exit Dropout-based BayesNNs
  10. Multi-Exit Enhancement
  11. Multi-Exit MCD-based BayesNNs
  12. Multi-Exit Masksembles
  13. Partial Dropout
  14. Compute Efficiency
  15. Transformation Framework
  16. ...and 11 more sections

Figures (6)

  • Figure 1: Overview of our four-phase transformation framework.
  • Figure 2: Difference between a single-exit BayesNN, a multi-exit NN and a multi-ext BayesNN.
  • Figure 3: Optimization flow.
  • Figure 4: Spatial and temporal mappings for Bayesian components.
  • Figure 5: Resource consumption of mask-based BayesNNs with LeNet, ResNet18 and VGG11 as network backbones. The quantization and custom number of channels are applied to fit models onto FPGAs.
  • ...and 1 more figures