RISC-V for HPC: Where we are and where we need to go

TL;DR

RISC-V has not yet gained broad traction in HPC, but the ExCALIBUR H&ES testbed provides free-access evaluation to accelerate adoption. The hardware landscape has progressed from embedded SBCs to the 64-core SG2042, with software stacks now supporting standard HPC workflows, though the performance gap to x86 remains substantial. The community, aided by the RISC-V HPC SIG, is growing, and ongoing efforts focus on hardware pipelines, accelerators, and unified programming models to boost energy efficiency. Continued collaboration and targeted investments in hardware and profiling tooling are essential to unlock RISC-V's potential in HPC.

Abstract

Funded by the UK ExCALIBUR H&ES exascale programme, since early 2022 we have provided a RISC-V testbed for HPC to offer free access for scientific software developers to experiment with RISC-V for their workloads. Based upon our experiences of providing access to RISC-V for the HPC community, and our involvement with the RISC-V community at large, in this extended abstract we summarise the current state of RISC-V for HPC and consider the high priority areas that should be addressed to help drive adoption.