Towards the Certification of Hybrid Architectures: Analysing Interference on Hardware Accelerators through PML

TL;DR

An overview of the standards applicable to the certification of hybrid platforms and an early mapping of their objectives to said platforms is presented.

Abstract

The emergence of Deep Neural Network (DNN) and machine learning-based applications paved the way for a new generation of hybrid hardware platforms. Hybrid platforms embed several cores and accelerators in a small package. However, in order to satisfy the Size, Weight and Power (SWaP) constraints, limited and shared resources are integrated. This paper presents an overview of the standards applicable to the certification of hybrid platforms and an early mapping of their objectives to said platforms. In particular, we consider how the classification of AMC20-152A for airborne electronic hardware applies to hybrid platforms. We also consider AMC20-193 for multi-core platforms, and how this standard fits different types of accelerators.

Figures (14)

• Figure 1: Overview of Phylog methodology
• Figure 2: Overview of the TI Keystone TCI6630K2L
• Figure 3: Simplified PML model for the Keystone platform
• Figure 4: Overview of the NVIDIA Jetson AGX Xavier
• Figure 5: Simplified PML model for the NVIDIA AGX Xavier

Theorems & Definitions (14)

• Example 1
• Example 2
• Example 3: of category \ref{['case-coupled']}
• Example 4: of category \ref{['case-passive']}
• Example 5: of category \ref{['case-semi-active']}
• Example 6: of category \ref{['case-semi-active']}
• Example 7: of category \ref{['case-active']}
• Example 8: of category \ref{['case-active']}
• Example 9: of category \ref{['case-active']}
• Example 10