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SAGA: Synthesis Augmentation with Genetic Algorithms for In-Memory Sequence Optimization

Andey Robins, Mike Borowczak

TL;DR

The paper tackles the data-movement bottleneck of von-Neumann architectures by leveraging processing-in-memory with MAGIC, reframing operation sequencing as a topological-sort permutation problem. It introduces SAGA, a genetic-algorithm–based synthesis augmentation that operates after netlist transcription to minimize the in-memory footprint and improve overall efficiency. Across 10 benchmark MAGIC circuits, SAGA achieves up to 52.8% memory-footprint reductions, up to 22.4% cycle improvements, and up to 128% gains in efficiency, with an average memory-cell reduction of about 32% and average efficiency improvement around 27.5%. The work demonstrates a viable, open-source CAD workflow where machine-learning–inspired optimization augments traditional design steps to enhance PIM performance, highlighting substantial practical impact for in-memory circuit evaluation.

Abstract

The von-Neumann architecture has a bottleneck which limits the speed at which data can be made available for computation. To combat this problem, novel paradigms for computing are being developed. One such paradigm, known as in-memory computing, interleaves computation with the storage of data within the same circuits. MAGIC, or Memristor Aided Logic, is an approach which uses memory circuits which physically perform computation through write operations to memory. Sequencing these operations is a computationally difficult problem which is directly correlated with the cost of solutions using MAGIC based in-memory computation. SAGA models the execution sequences as a topological sorting problem which makes the optimization well-suited for genetic algorithms. We then detail the formation and implementation of these genetic algorithms and evaluate them over a number of open circuit implementations. The memory-footprint needed for evaluating each of these circuits is decreased by up to 52% from existing, greedy-algorithm-based optimization solutions. Over the 10 benchmark circuits evaluated, these modifications lead to an overall improvement in the efficiency of in-memory circuit evaluation of 128% in the best case and 27.5% on average.

SAGA: Synthesis Augmentation with Genetic Algorithms for In-Memory Sequence Optimization

TL;DR

The paper tackles the data-movement bottleneck of von-Neumann architectures by leveraging processing-in-memory with MAGIC, reframing operation sequencing as a topological-sort permutation problem. It introduces SAGA, a genetic-algorithm–based synthesis augmentation that operates after netlist transcription to minimize the in-memory footprint and improve overall efficiency. Across 10 benchmark MAGIC circuits, SAGA achieves up to 52.8% memory-footprint reductions, up to 22.4% cycle improvements, and up to 128% gains in efficiency, with an average memory-cell reduction of about 32% and average efficiency improvement around 27.5%. The work demonstrates a viable, open-source CAD workflow where machine-learning–inspired optimization augments traditional design steps to enhance PIM performance, highlighting substantial practical impact for in-memory circuit evaluation.

Abstract

The von-Neumann architecture has a bottleneck which limits the speed at which data can be made available for computation. To combat this problem, novel paradigms for computing are being developed. One such paradigm, known as in-memory computing, interleaves computation with the storage of data within the same circuits. MAGIC, or Memristor Aided Logic, is an approach which uses memory circuits which physically perform computation through write operations to memory. Sequencing these operations is a computationally difficult problem which is directly correlated with the cost of solutions using MAGIC based in-memory computation. SAGA models the execution sequences as a topological sorting problem which makes the optimization well-suited for genetic algorithms. We then detail the formation and implementation of these genetic algorithms and evaluate them over a number of open circuit implementations. The memory-footprint needed for evaluating each of these circuits is decreased by up to 52% from existing, greedy-algorithm-based optimization solutions. Over the 10 benchmark circuits evaluated, these modifications lead to an overall improvement in the efficiency of in-memory circuit evaluation of 128% in the best case and 27.5% on average.
Paper Structure (13 sections, 2 figures, 3 tables)

This paper contains 13 sections, 2 figures, 3 tables.

Table of Contents

  1. Introduction
  2. Prior Work
  3. Emerging Paradigms
  4. Processing In-Memory
  5. Genetic Algorithms
  6. Methods
  7. Problem Formulation
  8. Netlist Transcription
  9. Genetic Operators
  10. Genetic Experiment
  11. Results
  12. Discussion
  13. Conclusion

Figures (2)

  • Figure 1: Sub-figure (a) details an execution graph with memory cell costs depending on the evaluation order of the graph. Two possible orders exist which fit the constraints described in Section \ref{['sec:problem-formulation']}. Processing vertex C before D has cost 3 while processing vertex D before C has cost 4 as illustrated in sub-figure (b).
  • Figure 2: The synthesis flow from benchmark circuit specifications to genetically optimized execution sequences.