Python-based DSL for generating Verilog model of Synchronous Digital Circuits

TL;DR

The paper presents a Python-based DSL that fills a niche between HLS and RTL by modeling synchronous digital circuits as transactions expressed in Serial/Parallel/Loop constructs and generating synthesizable Verilog with readable, preserved naming. Computations are organized into LeafSections that execute in a single clock, with Reg and Var semantics enabling both sequential and combinational behavior, and the framework supports automatic interface generation (e.g., AXI4/AXI-Lite). The approach is demonstrated through diverse case studies (e.g., PQC primitives with NTT and Keccak cores, matrix multiplication, stereo-vision, FFT, DWT, correlators, and BMO), comparing DSL-generated RTL to hand-crafted RTL/HLS implementations in terms of cycles, area, and throughput at 100 MHz. The results indicate that the DSL enables rapid hardware prototyping with reasonable overheads and clear hardware structure, while preserving the ability to integrate with standard FPGA toolchains; the authors also outline future work on conflict detection, breakpoints, and dynamic memory management, with source code available on GitHub. Overall, the work provides a practical bridge from Python-based modeling to synthesizable Verilog for synchronous circuits, supporting both design exploration and deployment in FPGA/ASIC flows.

Abstract

We have designed a Python-based Domain Specific Language (DSL) for modeling synchronous digital circuits. In this DSL, hardware is modeled as a collection of transactions -- running in series, parallel, and loops. When the model is executed by a Python interpreter, synthesizable and behavioural Verilog is generated as output, which can be integrated with other RTL designs or directly used for FPGA and ASIC flows. In this paper, we describe - 1) the language (DSL), which allows users to express computation in series/parallel/loop constructs, with explicit cycle boundaries, 2) the internals of a simple Python implementation to produce synthesizable Verilog, and 3) several design examples and case studies for applications in post-quantum cryptography, stereo-vision, digital signal processing and optimization techniques. In the end, we list ideas to extend this framework.

Figures (13)

• Figure 1: Python to Verilog
• Figure 2: A state-diagram for 'LeafSections' in 'add_sub' module
• Figure 3: Python DSL : Overall Flow
• Figure 4: Matrix Multiplication Hardware
• Figure 5: Clock Cycles taken for RTL Simulation