A nA-Range Area-Efficient Sub-100-ppm/°C Peaking Current Reference Using Forward Body Biasing in 0.11-$μ$m Bulk and 22-nm FD-SOI

TL;DR

This paper presents a nanoampere-range, area-efficient constant-with-temperature peaking current reference that uses forward body biasing to bias a resistor with the threshold-voltage difference ΔV_T between two subthreshold transistors. By combining a 2T ultra-low-power reference, leakage suppression, and trimming circuits for both the reference current and its temperature coefficient, the design achieves robust TC performance across process corners in two technologies: 0.11 μm bulk and 22-nm FD-SOI. Post-layout simulations show sub-5 nA currents with TC around 65–89 ppm/°C and LS on the order of 0.5–2.8 %/V, while measurements on the 22-nm FD-SOI implementation yield about 1.5 nA with TC ~89 ppm/°C and LS ~0.51 %/V, occupying only 0.00214 mm^2 and consuming ~2.87 nW. A comprehensive comparison to the state of the art reveals a ~12.9× FoM improvement over the closest fabricated competitor, driven by substantial area reductions and improved TC stability, with potential applications in IoT sensor nodes and ultra-low-power analog blocks.

Abstract

In recent years, the development of the Internet of Things (IoT) has prompted the search for nA-range current references that are simultaneously constrained to a small area and robust to process, voltage and temperature variations. Yet, such references have remained elusive, as existing architectures fail to reach a low temperature coefficient (TC) while minimizing silicon area. In this work, we propose a nA-range constant-with-temperature (CWT) peaking current reference, in which a resistor is biased by the threshold voltage difference between two transistors in weak inversion. This bias voltage is lower than in conventional architectures to cut down the silicon area occupied by the resistor and is obtained by forward body biasing one of the two transistors with an ultra-low-power voltage reference so as to reduce its threshold voltage. In addition, the proposed reference includes a circuit to suppress the leakage of parasitic diodes at high temperature, and two simple trimming mechanisms for the reference current and its TC. As the proposed design relies on the body effect, it has been validated in both 0.11-$μ$m bulk and 22-nm fully-depleted silicon-on-insulator, to demonstrate feasibility across different technology types. In post-layout simulation, the 0.11-$μ$m design generates a 5-nA current with a 65-ppm/°C TC and a 2.84-%/V line sensitivity (LS), while in measurement, the 22-nm design achieves a 1.5-nA current with an 89-ppm/°C TC and a 0.51-%/V LS. As a result of the low resistor bias voltage, the proposed references occupy a silicon area of 0.00954 mm$^2$ in 0.11 $μ$m (resp. 0.00214 mm$^2$ in 22 nm) at least 1.8$\times$ (resp. 8.2$\times$) smaller than fabricated nA-range CWT references, but with a TC improved by 6.1$\times$ (resp. 4.4$\times$).

Figures (29)

• Figure 1: (a) Requirements of current references in the context of the IoT, and landscape of existing CWT current references in terms of (b) temperature coefficient (TC) and (c) silicon area, highlighting the absence of both temperature-independent and area-efficient architectures in the nA range.
• Figure 2: Schematic of (a) the conventional PTAT peaking current reference and (b) the simplified proposed CWT one, which relies on the threshold voltage difference $\Delta V_T$ between $M_{1-2}$, obtained by forward body biasing $M_2$ with a 2T voltage reference ($M_{5-6}$). Operation principle illustrated with pre-layout simulations of (c) $\Delta V_{GS}$ and (d) $I_{REF}$ in 22-nm FD-SOI, for the conventional design with $J=K=2$, and the proposed one.
• Figure 3: Small-signal schematic of (a) the conventional PTAT PCR and (b) the proposed FBB addition to obtain a CWT reference current.
• Figure 4: The 2T voltage reference presents a nonideal behavior at low temperature, due to gate leakage, or to GIDL at high $\boldsymbol{V_{DS}}$. All figures correspond to 22-nm FD-SOI. Temperature dependence of (a) $V_{B2}$ in all process corners for a 2T voltage reference supplied at 1.8 V and implemented with 1-$\mu$m-long I/O nMOS, and (b) $\log(I_D)$ and $(g_m/I_D)$ at $V_{GS}$ = 0, and $\left(g_m/I_D\right)_{\textrm{max}}$, for two different $V_{DS}$ and for an I/O SLVT nMOS with $W$ = 3.89 $\mu$m and $L$ = 1 $\mu$m in the SS process corner.
• Figure 5: All figures correspond to the SS process corner with a fixed $V_{DS} = V_{GS,\textrm{max}}/2$. $\log(I_D)$, $g_m/I_D$ vs. $V_{GS}$ curves at -40$^\circ$C (a) in 0.11 $\mu$m for core LVT, RVT and HVT nMOS with $W$ = 0.5 $\mu$m and $L$ = 10.45 $\mu$m, and (c) in 22 nm for I/O SLVT and LVT nMOS with $W$ = 2 $\mu$m and $L$ = 8 $\mu$m. $\log(I_D)$ at $V_{GS}$ = 0 and -40, 25 and 85$^\circ$C, and $g_m/I_D$ at $V_{GS}$ = 0 and -40$^\circ$C as a percentage of $\left(g_m/I_D\right)_{\textrm{max}}$ (b) in 0.11 $\mu$m for a core LVT nMOS with $W$ = 0.5 $\mu$m and $L$ ranging from 0.12 to 50 $\mu$m, and (d) in 22 nm for an I/O SLVT nMOS with $W$ = 2 $\mu$m and $L$ ranging from 0.15 to 8 $\mu$m.