Superconductor bistable vortex memory for data storage and in-memory computing

TL;DR

This work introduces bistable vortex memory (BVM) for superconducting electronics as a dense, transformer-free, nonvolatile memory with zero static power and non-destructive readout. BVM uses two coupled SQUID loops to store data via circulating current direction, enabling high-speed operation up to tens of GHz and analog compute via current summation for in-memory MAC. A 32×32 memory array at 20 GHz demonstrates scalable storage, while an 8×8 crossbar illustrates analog accumulation suitable for neural networks. The paper also develops peripheral driver/readout circuits and demonstrates BVM-based crossbars performing multiplication and threshold-adjustable neuron tasks, highlighting substantial potential for fast, low-power SCE-based AI and HPC workloads.

Abstract

Superconductor electronics (SCE) is a promising complementary and beyond CMOS technology. However, despite its practical benefits, the realization of SCE logic faces a significant challenge due to the absence of dense and scalable nonvolatile memory designs. While various nonvolatile memory technologies, including Non-destructive readout, vortex transitional memory (VTM), and magnetic memory, have been explored, achieving a superconductor random-access memory (RAM) crossbar array remains challenging. This paper introduces a novel, nonvolatile, high-density, and scalable VTM cell design for SCE applications. Our proposed design addresses scaling issues while boasting zero static power consumption characteristics. Our design leverages current summation, enabling analog multiply-accumulate operations -an essential feature for many in-memory computational tasks. We demonstrate the efficacy of our approach with a 32 x 32 superconductor memory array operating at 20 GHz. This design effectively addresses scaling issues and utilizes current summation that can be used for analog multiply-accumulate operations. Additionally, we showcase the accumulation property of the memory through analog simulations conducted on an 8 x 8 superconductor crossbar array.

Figures (15)

• Figure 1: A pendulum with friction and a resistively and capacitively Shunted (Josephson) junction (RCSJ) model are shown with their respective equations. $A$, $B$, $\tilde{A}$, and $\tilde{B}$ are the constant coefficients dependent on the junction's geometry.
• Figure 2: BVM cell model with row and column access lines. Here, the storage loop is drawn in blue, whereas the readout loop is drawn in red. The junction $J_{M1}$ is the only shunted JJ here, and its symbol's vertical line represents the shunted resistor.
• Figure 3: a) The illustration of the BVM cell array with 32 rows and 32 columns. For a larger range of column bits, a column decoder may be necessary to select the correct address. b) the BVM cell's schematic consists of 4 JJs with row and column access lines. The inductances named $L_{P}$ correspond to the parasitics. The Storage Loop stores the data, and the read operation is performed with the help of the Readout Loop. ($R_{WL}$ = $R_{BL}$ = $R_{SE}$ = 20.0 $\Omega$, $R_{S}$ = 3.0 $\Omega$, $R_{SL}$ = 12.0 $\Omega$, $L_{PRWL}$ = $L_{PRBL}$ = $L_{PRSE}$ = $L_{PM}$ = $L_{S1}$ = $L_{S2}$ = $L_{PSL}$ = 0.5pH, $L_{M1}$ = 12.5pH, $L_{M2}$ = 24.5pH, $L_{M3}$ = 8.5pH, $L_{SL}$ = 0.4pH, $J_{M1}$ = $120\mu A$, $J_{M2}$ = $140\mu A$, $J_{S1}$ = $J_{S2}$ = $74\mu A$)
• Figure 4: JoSIM result of the BVM cell for the write operation $W$ and with all possible control signal combinations. The simulation is performed at 50 GHz.
• Figure 5: Simulation result of the BVM cell for the read operation R. The read is performed for each write operation W of '0' and '1', and the output current is observed on the SL. The simulation is performed at 50 GHz, and the load on the sense line is assigned as 12 non-switching junctions with 320 $\mu A$ critical current value each.