An origami Universal Turing Machine design
Michael Assis
TL;DR
This paper investigates whether origami can support universal computation by building a UTM using a NAND gate and memory. It presents a method to realize a NAND gate on a folding pattern by reinterpreting Bern and Hayes' NAE gadget, introducing rotation, duplication, and NOT gadgets built from a reflector element, and wiring three NAE gadgets with an auxiliary constant-zero signal. Scaling this gate alongside clocked D-type flip-flops enables memory and a CPU-like architecture, suggesting that, given an infinite sheet of paper and memory, a Universal Turing Machine could be implemented in origami. The discussion compares efficiency and rigidity considerations with a related recent result (Hull 2023), highlighting design trade-offs and limitations in rigid-foldable implementations.
Abstract
It has been known since 1996 that deciding whether a collection of creases on a piece of paper can be fully folded flat without causing self-intersection or adding new creases is an NP-Hard problem (Bern and Hayes). In their proof, a binary state was implemented as a pleat, with the state corresponding to the pleat layering order; states then interact via pleat intersections. Building on some of the machinery of their result, we will present a method for constructing an origami NAND logic gate, leading to a theoretical origami Universal Turing Machine.
