Hardware Implementation of Soft Mapper/Demappers in Iterative EP-based Receivers

TL;DR

The paper tackles the high complexity of MAP/ML detection in frequency-selective channels by proposing a hardware-implemented EP-based FD-SILE receiver for QPSK, 8-PSK, and 16-QAM. The approach uses FFT-based equalization and Expectation Propagation to approximate the posterior, with analytical approximations and fixed-point conversion enabling efficient FPGA implementation. Key contributions include (i) algorithmic simplifications for EP-based feedback, soft demapping, and soft mapping, (ii) a fixed-point conversion analysis showing near-floating-point performance, and (iii) a full FPGA prototyping on a PYNQ Z2 in an HIL setup with AFF3CT, demonstrating low resource usage across multiple constellations. The results confirm the practical viability of EP-based receivers in resource-constrained hardware and suggest paths for future enhancements such as constellation flexibility and turbo iterations. In particular, the EP framework facilitates robust feedback through LUT-based $C_{EP}$ and bitwise demapping/mapping, achieving competitive performance with modest hardware costs.$

Abstract

This paper presents a comprehensive study and implementations onto FPGA device of an Expectation Propagation (EP)-based receiver for QPSK, 8-PSK, and 16-QAM. To the best of our knowledge, this is the first for this kind of receiver. The receiver implements a Frequency Domain (FD) Self-Iterated Linear Equalizer (SILE), where EP is used to approximate the true posterior distribution of the transmitted symbols with a simpler distribution. Analytical approximations for the EP feedback generation process and the three constellations are applied to lessen the complexity of the soft mapper/demapper architectures. The simulation results demonstrate that the fixed-point version performs comparably to the floating-point. Moreover, implementation results show the efficiency in terms of FPGA resource usage of the proposed architecture.

Figures (5)

• Figure 1: FD SILE functional structure.
• Figure 2: Constellation bit values.
• Figure 3: Simplified bitwise soft demapper.
• Figure 4: Impact in terms of performance of simplification and fixed-point conversion.
• Figure 5: Simplified EP-based FD-SILE FPGA and HIL Block Diagram.