Large Language Model (LLM) for Standard Cell Layout Design Optimization

TL;DR

This work tackles the challenge of producing competitive PPA and routable standard-cell layouts at a 2 nm node by introducing a Large Language Model–driven optimization workflow. The approach combines domain-knowledge extraction, specialized netlist tooling, and a ReAct reasoning loop to incrementally generate high-quality device clusters that improve routing and area efficiency, guided by designers. Experimental results on industrial 2 nm sequential cells show up to a 19.4% reduction in cell area and 100% LVS/DRC cleanliness in tested cases, with average area reductions around 4.65%. The study demonstrates a practical pathway for integrating LLMs into EDA to assist with clustering-aware layout optimization and routability debugging.

Abstract

Standard cells are essential components of modern digital circuit designs. With process technologies advancing toward 2nm, more routability issues have arisen due to the decreasing number of routing tracks, increasing number and complexity of design rules, and strict patterning rules. The state-of-the-art standard cell design automation framework is able to automatically design standard cell layouts in advanced nodes, but it is still struggling to generate highly competitive Performance-Power-Area (PPA) and routable cell layouts for complex sequential cell designs. Consequently, a novel and efficient methodology incorporating the expertise of experienced human designers to incrementally optimize the PPA of cell layouts is highly necessary and essential. High-quality device clustering, with consideration of netlist topology, diffusion sharing/break and routability in the layouts, can reduce complexity and assist in finding highly competitive PPA, and routable layouts faster. In this paper, we leverage the natural language and reasoning ability of Large Language Model (LLM) to generate high-quality cluster constraints incrementally to optimize the cell layout PPA and debug the routability with ReAct prompting. On a benchmark of sequential standard cells in 2nm, we demonstrate that the proposed method not only achieves up to 19.4% smaller cell area, but also generates 23.5% more LVS/DRC clean cell layouts than previous work. In summary, the proposed method not only successfully reduces cell area by 4.65% on average, but also is able to fix routability in the cell layout designs.

Figures (8)

• Figure 1: An illustration of the PPA and routability optimization loop includes an agent with design expertise, adjusted cluster constraints, and a standard cell layout automation framework (i.e., NVCell).
• Figure 2: Standard cell layout design domain knowledge assessment of existing LLM on: (a) SPICE language, (b) cluster constraint, and (c) physical layout.
• Figure 3: Overview of LLM for Standard cell layout design optimization flow
• Figure 4: An example of ReAct steps of Thought-Action-Observation for standard cell layout design optimization.
• Figure 5: The cluster constraints and cell layouts of 2 nm weak transformer cluster modelho2024novel, and proposed method of Seq3 cell. The proposed method successfully reduce the CW, and TWL by 18.18%, and 16.48%, respectively.