Apparate: Evading Memory Hierarchy with GodSpeed Wireless-on-Chip

TL;DR

The paper addresses the memory-hierarchy bottleneck by exploring wireless on-chip interconnects as a path to direct CPU-to-DRAM access. It introduces Apparate and Apparatemagic as concepts leveraging GodSpeed wireless transceivers and Wireless Network-on-Chip (WiNoC) to potentially evict traditional caches. Through extrapolations to 2050, the authors argue that DRAM bandwidth and WiNoC capabilities could rival or exceed cache bandwidth and area, motivating a shift away from caches toward a wireless memory path. The work outlines feasibility questions, such as coherence handling and thermal implications, and emphasizes the potential for substantial gains in latency and efficiency if such a vision can be realized. Overall, it presents a provocative roadmap for rethinking memory architecture around high-bandwidth, chip-scale wireless communications.

Abstract

The rapid advancements in memory systems, CPU technology, and emerging technologies herald a transformative potential in computing, promising to revolutionize memory hierarchies. Innovations in DDR memory are delivering unprecedented bandwidth, while advancements in on-chip wireless technology are reducing size and increasing speed. The introduction of godspeed wireless transceivers on chip, alongside near high-speed DRAM, is poised to directly facilitate memory requests. This integration suggests the potential for eliminating traditional memory hierarchies, offering a new paradigm in computing efficiency and speed. These developments indicate a near-future where computing systems are significantly more responsive and powerful, leveraging direct, high-speed memory access mechanisms.

Figures (7)

• Figure 1: Yet another Moore's Law graph towards 2050.
• Figure 2: Processor clock rate towards 2050.
• Figure 3: On-chip cache area towards 2050.
• Figure 4: DDR "N" bandwidth towards 2050.
• Figure 5: GodSpeed WiNoC bandwidth towards 2050.