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A Gigabit, DMA-enhanced Open-Source Ethernet Controller for Mixed-Criticality Systems

Chaoqun Liang, Alessandro Ottaviano, Thomas Benz, Mattia Sinigaglia, Luca Benini, Angelo Garofalo, Davide Rossi

TL;DR

The paper addresses the need for a high-performance, open-source Ethernet IP suitable for mixed-criticality automotive and embedded systems, identifying limitations of existing solutions like LowRISC. It introduces a bufferless 1 Gbps Ethernet IP with an autonomous iDMA that directly bridges AXI and AXI Stream, coupled with CDC FIFOs and width adapters, and provides runtime configurability. The approach is validated by integrating the IP into Cheshire and HULK-V platforms, with FPGA-based latency measurements and GF22nm-area synthesis showing substantial latency reductions (~63%) and a dramatic area reduction (~88%). The work enables practical, open-source exploration and prototyping of heterogeneous, AXI-based systems for mixed-criticality networking in automotive and aerospace domains.

Abstract

The ongoing revolution in application domains targeting autonomous navigation, first and foremost automotive "zonalization", has increased the importance of certain off-chip communication interfaces, particularly Ethernet. The latter will play an essential role in next-generation vehicle architectures as the backbone connecting simultaneously and instantaneously the zonal/domain controllers. There is thereby an incumbent need to introduce a performant Ethernet controller in the open-source HW community, to be used as a proxy for architectural explorations and prototyping of mixed-criticality systems (MCSs). Driven by this trend, in this work, we propose a fully open-source, DMA-enhanced, technology-agnostic Gigabit Ethernet architecture that overcomes the limitations of existing open-source architectures, such as Lowrisc's Ethernet, often tied to FPGA implementation, performance-bound by sub-optimal design choices such as large memory buffers, and in general not mature enough to bridge the gap between academia and industry. Besides the area advantage, the proposed design increases packet transmission speed up to almost 3x compared to Lowrisc's and is validated through implementation and FPGA prototyping into two open-source, heterogeneous MCSs.

A Gigabit, DMA-enhanced Open-Source Ethernet Controller for Mixed-Criticality Systems

TL;DR

The paper addresses the need for a high-performance, open-source Ethernet IP suitable for mixed-criticality automotive and embedded systems, identifying limitations of existing solutions like LowRISC. It introduces a bufferless 1 Gbps Ethernet IP with an autonomous iDMA that directly bridges AXI and AXI Stream, coupled with CDC FIFOs and width adapters, and provides runtime configurability. The approach is validated by integrating the IP into Cheshire and HULK-V platforms, with FPGA-based latency measurements and GF22nm-area synthesis showing substantial latency reductions (~63%) and a dramatic area reduction (~88%). The work enables practical, open-source exploration and prototyping of heterogeneous, AXI-based systems for mixed-criticality networking in automotive and aerospace domains.

Abstract

The ongoing revolution in application domains targeting autonomous navigation, first and foremost automotive "zonalization", has increased the importance of certain off-chip communication interfaces, particularly Ethernet. The latter will play an essential role in next-generation vehicle architectures as the backbone connecting simultaneously and instantaneously the zonal/domain controllers. There is thereby an incumbent need to introduce a performant Ethernet controller in the open-source HW community, to be used as a proxy for architectural explorations and prototyping of mixed-criticality systems (MCSs). Driven by this trend, in this work, we propose a fully open-source, DMA-enhanced, technology-agnostic Gigabit Ethernet architecture that overcomes the limitations of existing open-source architectures, such as Lowrisc's Ethernet, often tied to FPGA implementation, performance-bound by sub-optimal design choices such as large memory buffers, and in general not mature enough to bridge the gap between academia and industry. Besides the area advantage, the proposed design increases packet transmission speed up to almost 3x compared to Lowrisc's and is validated through implementation and FPGA prototyping into two open-source, heterogeneous MCSs.
Paper Structure (11 sections, 4 figures)

This paper contains 11 sections, 4 figures.

Table of Contents

  1. Introduction
  2. Architecture
  3. Ethernet Media Access Controller (MAC) with Reduced Gigabit Media Independent Interface (RGMII) xilinx2023xapp692
  4. Direct Memory Access (DMA)
  5. Clock Domain Crossing (CDC) FIFOs
  6. Up/Down Sizers
  7. Configuration Registers
  8. Results
  9. Performance test
  10. Area test
  11. Conclusion

Figures (4)

  • Figure 1: LowRisc Ethernet Design
  • Figure 2: Bufferless Ethernet Design
  • Figure 3: Performance Comparison of Buffer and Bufferless Ethernet Design
  • Figure 4: Buffer and Bufferless Area Info in GF22