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Identifying Bottlenecks of NISQ-friendly HHL algorithms

Marc Andreu Marfany, Alona Sakhnenko, Jeanette Miriam Lorenz

TL;DR

This paper empirically analyzes bottlenecks in NISQ-friendly HHL algorithms by focusing on the QPE subroutine and its Iterative variant (IQPE). Using Qiskit and Scipy to build QPE/IQPE circuits and IBM Brisbane-like noise models, the study tests how problem size, input sparsity, and noise sources affect performance, with noise-mitigation techniques such as Qiskit readout and M3. The findings show that current readout mitigation is insufficient to recover useful results even for small instances, and that the main bottleneck arises from precision-driven scaling of the unitary evolution and the associated gate counts. The work highlights a narrow practical window for QPE-inspired approaches on NISQ devices and suggests future directions including targeted noise-mitigation strategies and non-time-evolution-based linear solver approaches to widen applicability.

Abstract

Quantum computing promises enabling solving large problem instances, e.g. large linear equation systems with HHL algorithm, once the hardware stack matures. For the foreseeable future quantum computing will remain in the so-called NISQ era, in which the algorithms need to account for the flaws of the hardware such as noise. In this work, we perform an empirical study to test scaling properties and directly related noise resilience of the the most resources-intense component of the HHL algorithm, namely QPE and its NISQ-adaptation Iterative QPE. We explore the effectiveness of noise mitigation techniques for these algorithms and investigate whether we can keep the gate number low by enforcing sparsity constraints on the input or using circuit optimization techniques provided by Qiskit package. Our results indicate that currently available noise mitigation techniques, such as Qiskit readout and Mthree readout packages, are insufficient for enabling results recovery even in the small instances tested here. Moreover, our results indicate that the scaling of these algorithms with increase in precision seems to be the most substantial obstacle. These insights allowed us to deduce an approximate bottleneck for algorithms that consider a similar time evolution as QPE. Such observations provide evidence of weaknesses of such algorithms on NISQ devices and help us formulate meaningful future research directions.

Identifying Bottlenecks of NISQ-friendly HHL algorithms

TL;DR

This paper empirically analyzes bottlenecks in NISQ-friendly HHL algorithms by focusing on the QPE subroutine and its Iterative variant (IQPE). Using Qiskit and Scipy to build QPE/IQPE circuits and IBM Brisbane-like noise models, the study tests how problem size, input sparsity, and noise sources affect performance, with noise-mitigation techniques such as Qiskit readout and M3. The findings show that current readout mitigation is insufficient to recover useful results even for small instances, and that the main bottleneck arises from precision-driven scaling of the unitary evolution and the associated gate counts. The work highlights a narrow practical window for QPE-inspired approaches on NISQ devices and suggests future directions including targeted noise-mitigation strategies and non-time-evolution-based linear solver approaches to widen applicability.

Abstract

Quantum computing promises enabling solving large problem instances, e.g. large linear equation systems with HHL algorithm, once the hardware stack matures. For the foreseeable future quantum computing will remain in the so-called NISQ era, in which the algorithms need to account for the flaws of the hardware such as noise. In this work, we perform an empirical study to test scaling properties and directly related noise resilience of the the most resources-intense component of the HHL algorithm, namely QPE and its NISQ-adaptation Iterative QPE. We explore the effectiveness of noise mitigation techniques for these algorithms and investigate whether we can keep the gate number low by enforcing sparsity constraints on the input or using circuit optimization techniques provided by Qiskit package. Our results indicate that currently available noise mitigation techniques, such as Qiskit readout and Mthree readout packages, are insufficient for enabling results recovery even in the small instances tested here. Moreover, our results indicate that the scaling of these algorithms with increase in precision seems to be the most substantial obstacle. These insights allowed us to deduce an approximate bottleneck for algorithms that consider a similar time evolution as QPE. Such observations provide evidence of weaknesses of such algorithms on NISQ devices and help us formulate meaningful future research directions.
Paper Structure (29 sections, 9 equations, 7 figures, 1 table)

This paper contains 29 sections, 9 equations, 7 figures, 1 table.

Figures (7)

  • Figure 1: Fidelity heatmaps for the output distributions from the QPE and IQPE algorithms with respect to the uniform distribution in a noiseless environment. The axes correspond the number of clock qubits $n_{\text{c}}$ and the sparsity level $s$ of the input matrix $A$.
  • Figure 2: Fidelities of the output distribution from QPE and IQPE with respect to the sparsity level. The dimension of the matrix chosen was 8x8 and $n_{\text{c}}=8$
  • Figure 3: Fidelities of the output distribution vs the depolarising error figure \ref{['p_r_out_0.0001_reset_0.003']}, readout error figure \ref{['depol_noise_1e-5_p_reset_0.003']} and reset error figure \ref{['depol_error_1e-6_p_r_out_1e-4']}. In the left corresponds the QPE algorithm and on the right for the Iterative QPE. The pink line marks the fidelity for a noiseless simulation. In every case is shown the fidelity for various levels of optimization of the circuit. The dimension of the matrix was set to be 8x8 with a 35 $\%$ of sparsity level and with four clock qubits.
  • Figure 4: Total number of gates of the circuit as function of the sparsity level of the matrix A. The dimension of the matrix chosen is 8x8 and $n_{\text{c}}=8$.
  • Figure 5: Number of gates (in a logarithm scale) vs the number of times that we apply the controlled Unitary, cU. Although overlapped, it is shown the number of gates depending on the optimisation level of the circuit. The dimension of the matrix chosen was 8x8 and $n_{\text{c}}=8$. The sparsity level of the matrix is 0 $\%$.
  • ...and 2 more figures