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Practical Boolean Decomposition for Delay-driven LUT Mapping

Alessandro Tempia Calvino, Alan Mishchenko, Giovanni De Micheli, Robert Brayton

TL;DR

This paper presents a novel fast and versatile technique of ACD suitable for delay optimization to compute two-level decompositions into a variable number of LUTs and enhance delay-driven LUT mapping by performing ACD on the fly.

Abstract

Ashenhurst-Curtis decomposition (ACD) is a decomposition technique used, in particular, to map combinational logic into lookup tables (LUTs) structures when synthesizing hardware designs. However, available implementations of ACD suffer from excessive complexity, search-space restrictions, and slow run time, which limit their applicability and scalability. This paper presents a novel fast and versatile technique of ACD suitable for delay optimization. We use this new formulation to compute two-level decompositions into a variable number of LUTs and enhance delay-driven LUT mapping by performing ACD on the fly. Compared to state-of-the-art technology mapping, experiments on heavily optimized benchmarks demonstrate an average delay improvement of 12.39%, and area reduction of 2.20% with affordable run time. Additionally, our method improves 4 of the best delay results in the EPFL synthesis competition without employing design-space exploration techniques.

Practical Boolean Decomposition for Delay-driven LUT Mapping

TL;DR

This paper presents a novel fast and versatile technique of ACD suitable for delay optimization to compute two-level decompositions into a variable number of LUTs and enhance delay-driven LUT mapping by performing ACD on the fly.

Abstract

Ashenhurst-Curtis decomposition (ACD) is a decomposition technique used, in particular, to map combinational logic into lookup tables (LUTs) structures when synthesizing hardware designs. However, available implementations of ACD suffer from excessive complexity, search-space restrictions, and slow run time, which limit their applicability and scalability. This paper presents a novel fast and versatile technique of ACD suitable for delay optimization. We use this new formulation to compute two-level decompositions into a variable number of LUTs and enhance delay-driven LUT mapping by performing ACD on the fly. Compared to state-of-the-art technology mapping, experiments on heavily optimized benchmarks demonstrate an average delay improvement of 12.39%, and area reduction of 2.20% with affordable run time. Additionally, our method improves 4 of the best delay results in the EPFL synthesis competition without employing design-space exploration techniques.
Paper Structure (19 sections, 4 equations, 4 figures, 4 tables, 1 algorithm)

This paper contains 19 sections, 4 equations, 4 figures, 4 tables, 1 algorithm.

Table of Contents

  1. Introduction
  2. Preliminaries
  3. Definitions
  4. Ashenhurst-Curtis decomposition
  5. FPGA technology mapping
  6. Improvements to ACD
  7. Finding a feasible decomposition
  8. Functional encoding and support minimization
  9. Technology mapping with ACD
  10. Delay-oriented ACD
  11. Checking the existence of a decomposition
  12. Computing the decomposition
  13. LUT mapping with ACD
  14. Experiments
  15. Decomposition success rate
  16. ...and 4 more sections

Figures (4)

  • Figure 1: ACD of an $8$-input Boolean function into three $5$-input LUTs with a $5$-variable bound set (BS), a $1$-variable shared set (SS), and a $2$-variable free set (FS).
  • Figure 2: Truth table representations and their encoding, cofactor extraction w.r.t. the two most significant variables, and variable swapping of $x_0$ with $x_2$.
  • Figure 3: Illustrating the AC decomposition of a Boolean function
  • Figure 4: Covering table to solve the encoding problem.