Superconducting qubits in the millions: the potential and limitations of modularity

TL;DR

This paper presents an architectural model of a potential FTQC based on superconducting qubits, divided into discrete modules and interconnected via coherent links, and employs a resource estimation framework and software tool to assess the physical resources required to execute specific quantum algorithms compiled into their graph-state form and arranged onto a modular superconducting hardware architecture.

Abstract

The development of fault-tolerant quantum computers (FTQCs) is receiving increasing attention within the quantum computing community. Like conventional digital computers, FTQCs, which utilize error correction and millions of physical qubits, have the potential to address some of humanity's grand challenges. However, accurate estimates of the tangible scale of future FTQCs, based on transparent assumptions, are uncommon. How many physical qubits are necessary to solve a practical problem intractable for classical hardware? What costs arise from distributing quantum computation across multiple machines? This paper presents an architectural model of a potential FTQC based on superconducting qubits, divided into discrete modules and interconnected via coherent links. We employ a resource estimation framework and software tool to assess the physical resources required to execute specific quantum algorithms compiled into their graph-state form and arranged onto a modular superconducting hardware architecture. Our tool can predict the size, power consumption, and execution time of these algorithms based on explicit assumptions about the system's physical layout, thermal load, and modular connectivity. We assess the resources needed for quantum computation examples that serve as building blocks of proposed applications, quantifying the architectural bottlenecks and trade-offs that remain to be addressed to deliver utility.

Figures (16)

• Figure 1: (top) Fault-tolerant algorithm execution involves segmenting the application into logical Clifford and non-Clifford portions. Clifford operations are performed using a set of measurements on logical memory qubits, facilitated by auxiliary buses. Because measurement outcomes are probabilistic, classical feedback and feedforward are incorporated into operation schedules. Non-Clifford portions are implemented using $T$-states distilled by $T$-factories. (bottom) This results in our proposed logical micro-architecture, detailed in \ref{['sec:hardware-architecture']}. The architecture includes graph preparation, consumption, local $T$-factories, $T$-state and Bell-state queuing, with some parallelization. We arrange logical qubits on a square lattice of rotated surface code patches of distance-$d$ made of physical qubits. A left portion of the module is allocated for the logical memory (blue tiles). It also contains an "auxiliary bus" of logical auxiliary qubits needed for graph preparation, consumption, $T$, and Bell-state routing. Yellow tiles represent the auxiliary bus, followed by lighter-yellow "auxiliary$+$ bus" required for routing. To its left, a separate bus is designated for continuous queuing of $T$-states distilled in an array of $T$-factories on the opposite side of the module (teal tiles) — see also Parameters 6 and 8 of \ref{['supp:RRE-outputs']}. This architecture can be distributed across multiple modules, provided they are coherently connected via the auxiliary bus and each module consumes local $T$-states.
• Figure 2: The high-level graph state processing cycle: the algorithm is divided into time-sliced widgets that are interleaved across two module sets in the time direction. Each set, consisting of three modules in this example, interleaves graph-state preparation with graph-state consumption. Graph-state preparation consists solely of Clifford operations (blue), while consumption utilizes $T$-state resources (purple). Teleportation moves logical state between module sets, from the output of one graph-state consumption to the input of the next. Teleportation is also used to facilitate operations that cross module boundaries within the set.
• Figure 3: The high-level macro-architecture consists of two sets of 1-million physical qubit (1MQ) modules arranged like the legs of a ladder. Following the example in \ref{['fig:graph-proc-cycle']}, each leg contains three modules, each following the layout of \ref{['fig:log-layout']}(bottom). Portions of the algorithm are divided and executed solely within modules on the same leg, where intra-module interactions with high connectivity and short gate times dominate. All modules communicate via width-$d$ "coherent interconnects" (or links) at a lower rate and with reduced connectivity, used only for graph preparation (vertical interconnects) and state handover (horizontal interconnects).
• Figure 4: A schematic layout for the required components to couple superconducting qubits through tunable couplers in a surface code layout. In this example, we demonstrated the essential components: qubits, readout resonators, tunable couplers, and IO pins. Each physical qubit and coupler requires a single control line, their respective ground connections, and an additional RF line for multiplexed readout shared among 10 qubits. This limits the physical qubit pitch to match that of the signal lines. A qubit-to-qubit pitch at three times the signal line pitch has sufficient IO pins to accommodate this.
• Figure 5: Physical qubit chips are tiled on a carrier. Tunable couplers manage two-qubit gates on physical qubits within the chip. ICC refers to "inter-chip coupler."