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fSEAD: a Composable FPGA-based Streaming Ensemble Anomaly Detection Library

Binglei Lou, David Boland, Philip H. W. Leong

TL;DR

The paper addresses the need for scalable, low-latency anomaly detection in streaming data by introducing fSEAD, a composable FPGA-based SEAD library. It combines an HLS-based Module Generator with a run-time fabric of pblocks interconnected by AXI switches and reconfigurable via Dynamic Function eXchange (DFX) to assemble diverse detector ensembles including Loda, RS-Hash, and xStream. The main contributions are the first FPGA-based SEAD framework enabling runtime composition of multiple detectors without recompilation, hardware implementations of three state-of-the-art detectors, and an open-source design demonstrating $3\times$ to $8\times$ CPU speedups with configurable trade-offs in accuracy and power. This work enables flexible, scalable hardware acceleration for real-time anomaly detection with tunable resource use and reconfiguration overhead.

Abstract

Machine learning ensembles combine multiple base models to produce a more accurate output. They can be applied to a range of machine learning problems, including anomaly detection. In this paper, we investigate how to maximize the composability and scalability of an FPGA-based streaming ensemble anomaly detector (fSEAD). To achieve this, we propose a flexible computing architecture consisting of multiple partially reconfigurable regions, pblocks, which each implement anomaly detectors. Our proof-of-concept design supports three state-of-the-art anomaly detection algorithms: Loda, RS-Hash and xStream. Each algorithm is scalable, meaning multiple instances can be placed within a pblock to improve performance. Moreover, fSEAD is implemented using High-level synthesis (HLS), meaning further custom anomaly detectors can be supported. Pblocks are interconnected via an AXI-switch, enabling them to be composed in an arbitrary fashion before combining and merging results at run-time to create an ensemble that maximizes the use of FPGA resources and accuracy. Through utilizing reconfigurable Dynamic Function eXchange (DFX), the detector can be modified at run-time to adapt to changing environmental conditions. We compare fSEAD to an equivalent central processing unit (CPU) implementation using four standard datasets, with speed-ups ranging from $3\times$ to $8\times$.

fSEAD: a Composable FPGA-based Streaming Ensemble Anomaly Detection Library

TL;DR

The paper addresses the need for scalable, low-latency anomaly detection in streaming data by introducing fSEAD, a composable FPGA-based SEAD library. It combines an HLS-based Module Generator with a run-time fabric of pblocks interconnected by AXI switches and reconfigurable via Dynamic Function eXchange (DFX) to assemble diverse detector ensembles including Loda, RS-Hash, and xStream. The main contributions are the first FPGA-based SEAD framework enabling runtime composition of multiple detectors without recompilation, hardware implementations of three state-of-the-art detectors, and an open-source design demonstrating to CPU speedups with configurable trade-offs in accuracy and power. This work enables flexible, scalable hardware acceleration for real-time anomaly detection with tunable resource use and reconfiguration overhead.

Abstract

Machine learning ensembles combine multiple base models to produce a more accurate output. They can be applied to a range of machine learning problems, including anomaly detection. In this paper, we investigate how to maximize the composability and scalability of an FPGA-based streaming ensemble anomaly detector (fSEAD). To achieve this, we propose a flexible computing architecture consisting of multiple partially reconfigurable regions, pblocks, which each implement anomaly detectors. Our proof-of-concept design supports three state-of-the-art anomaly detection algorithms: Loda, RS-Hash and xStream. Each algorithm is scalable, meaning multiple instances can be placed within a pblock to improve performance. Moreover, fSEAD is implemented using High-level synthesis (HLS), meaning further custom anomaly detectors can be supported. Pblocks are interconnected via an AXI-switch, enabling them to be composed in an arbitrary fashion before combining and merging results at run-time to create an ensemble that maximizes the use of FPGA resources and accuracy. Through utilizing reconfigurable Dynamic Function eXchange (DFX), the detector can be modified at run-time to adapt to changing environmental conditions. We compare fSEAD to an equivalent central processing unit (CPU) implementation using four standard datasets, with speed-ups ranging from to .
Paper Structure (18 sections, 20 figures, 13 tables, 4 algorithms)

This paper contains 18 sections, 20 figures, 13 tables, 4 algorithms.

Table of Contents

  1. Introduction
  2. Background and Related Work
  3. Streaming Anomaly Detection
  4. Ensembles of multiple anomaly detectors
  5. Dynamic Partial Reconfiguration and Partial Overlays
  6. Literature Review
  7. Design
  8. Module Generator
  9. DFX Tool Flow
  10. Composable Infrastructure
  11. FPGA Implementation
  12. Results
  13. Test Platform
  14. Sub-detectors and Ensemble Accuracy
  15. Pblock Assignment and FPGA Implementation
  16. ...and 3 more sections

Figures (20)

  • Figure 1: Sample Architecture for SEAD Methods.
  • Figure 2: Basic Premise of Partial Reconfiguration.
  • Figure 3: Overview of the fSEAD Framework.
  • Figure 4: An Example of A Hash-based AD Hardware Structure in fSEAD.
  • Figure 5: An Example of Xilinx Partial Reconfiguration Tool flow.
  • ...and 15 more figures