Energy-Efficient Approximate Full Adders Applying Memristive Serial IMPLY Logic For Image Processing

TL;DR

This work targets memory and power bottlenecks by combining memristive memory with approximate computing through IMPLY-based in-memory processing. It introduces four memristive approximate full adders: three ICIS variants with Inexact Carry and Inexact Sum, and ECIS with Exact Carry and Inexact Sum, achieving up to $20$–$75\%$ energy savings and up to $48\%$ fewer computation steps versus exact adders, while controlling error via multiple metrics. The adders are analyzed at circuit and error levels and validated in three image-processing tasks (image addition, motion detection, grayscale filtering), demonstrating acceptable image quality (PSNR often above 30 dB) for error-tolerant applications. Two Figures of Merit quantify circuit-efficiency vs. accuracy, guiding the trade-offs: ICIS variants offer strong energy-delay-accuracy gains, while ECIS provides the best accuracy, particularly when error propagation must be minimized. Overall, the paper demonstrates practical, energy-efficient IMPLY-based memristive adders suitable for near-memory processing in image pipelines.

Abstract

Researchers and designers are facing problems with memory and power walls, considering the pervasiveness of Von-Neumann architecture in the design of processors and the problems caused by reducing the dimensions of deep sub-micron transistors. Memristive Approximate Computing (AC) and In-Memory Processing (IMP) can be promising solutions to these problems. We have tried to solve the power and memory wall problems by presenting the implementation algorithm of four memristive approximate full adders applying the Material Implication (IMPLY) method. The proposed circuits reduce the number of computational steps by up to 40% compared to the state-of-the-art. The energy consumption of the proposed circuits improves over the previous exact ones by 49%-75% and over the approximate full adders by up to 41%. Multiple error evaluation criteria evaluate the computational accuracy of the proposed approximate full adders in three scenarios in the 8-bit approximate adder structure. The proposed approximate full adders are evaluated in three image processing applications in three scenarios. The results of application-level simulation indicate that the four proposed circuits can be applied in all three scenarios, considering the acceptable image quality metrics of the output images.

Figures (11)

• Figure 1: (a) Circuit design of a memristive IMPLY logic gate ref3, and (b) the serial architecture of an IMPLY-based n-bit adder ref3.
• Figure 2: Schematic representation of ICIS1, ICIS2, and ICIS3.
• Figure 3: Schematic representation of ECIS.
• Figure 4: ICIS1's waveforms: (a) $A_{in}B_{in}C_{in}$=$"001"$, and (b) $A_{in}B_{in}C_{in}$=$"110"$.
• Figure 5: ICIS2's waveforms: (a) $A_{in}B_{in}C_{in}$=$"000"$, and (b) $A_{in}B_{in}C_{in}$=$"110"$.