Look-Up Table based Neural Network Hardware

TL;DR

The paper tackles the high power and area costs of digital neural accelerators by introducing LUT-NA, a programmable LUT-based framework that precomputes MAC results to accelerate inference while avoiding analog noise. It combines a divide-and-conquer LUT strategy with Lottery Ticket Pruning to drastically reduce MAC operations and hardware, and further extends efficiency with a storage-optimized, approximated variant (A-LUT-NA) and a mixed-precision scheme. Empirical results on CIFAR-10 with LTP-pruned VGG11/19, ResNet variants, and GoogleNet show dramatic hardware savings: up to 29.54x area reduction and 3.34x energy reduction versus traditional LUTs, and up to 1.23x area and 1.80x energy reduction versus conventional digital MACs for 8-bit activations and 9-bit weights, with minimal accuracy loss (~1%). The work demonstrates how scalable LUT-based neural acceleration can reach practical edge applicability and outlines future directions for broader models and memory technologies.

Abstract

Traditional digital implementations of neural accelerators are limited by high power and area overheads, while analog and non-CMOS implementations suffer from noise, device mismatch, and reliability issues. This paper introduces a CMOS Look-Up Table (LUT)-based Neural Accelerator (LUT-NA) framework that reduces the power, latency, and area consumption of traditional digital accelerators through pre-computed, faster look-ups while avoiding noise and mismatch of analog circuits. To solve the scalability issues of conventional LUT-based computation, we split the high-precision multiply and accumulate (MAC) operations into lower-precision MACs using a divide-and-conquer-based approach. We show that LUT-NA achieves up to $29.54\times$ lower area with $3.34\times$ lower energy per inference task than traditional LUT-based techniques and up to $1.23\times$ lower area with $1.80\times$ lower energy per inference task than conventional digital MAC-based techniques (Wallace Tree/Array Multipliers) without retraining and without affecting accuracy, even on lottery ticket pruned (LTP) models that already reduce the number of required MAC operations by up to 98%. Finally, we introduce mixed precision analysis in LUT-NA framework for various LTP models (VGG11, VGG19, Resnet18, Resnet34, GoogleNet) that achieved up to $32.22\times$-$50.95\times$ lower area across models with $3.68\times$-$6.25\times$ lower energy per inference than traditional LUT-based techniques, and up to $1.35\times$-$2.14\times$ lower area requirement with $1.99\times$-$3.38\times$ lower energy per inference across models as compared to conventional digital MAC-based techniques with $\sim$1% accuracy loss.

Figures (9)

• Figure 1: Example 4b $\times$ 4b LUT based multiplier using D&C
• Figure 2: The number 0 has a significantly higher probability of occurrence w.r.t. other possible activation values. Hence, the number 0 also has the highest probability of being the 6b product in the LSB side multiplication.
• Figure 3: Proposed LUT-NA framework using the storage-optimized and approximated D&C approach (A-LUT-NA)
• Figure 4: Bit-resolution requirement for activations and weight on the LTP pruned VGG11 and Resnet18 models, which illustrates that 8b activations and 9b weights (1 sign bit) are needed to reach the baseline accuracy of the models.
• Figure 5: 8b LUT-NA used in this paper, utilizing the D&C approach and storage-optimized and approximated D&C approach. 1 additional bit is reserved for the sign.