LLM-Enhanced Bayesian Optimization for Efficient Analog Layout Constraint Generation
Guojin Chen, Keren Zhu, Seunggeun Kim, Hanqing Zhu, Yao Lai, Bei Yu, David Z. Pan
TL;DR
This work addresses the challenge of automated analog layout synthesis, which is traditionally manual and time-consuming, by introducing LLANA, a framework that enhances Bayesian optimization with Large Language Models. LLANA leverages in-context learning to create a surrogate model and employs a conditional sampling mechanism to generate high-potential design points, aiming to reduce data requirements while maintaining performance. Empirical results show LLANA achieving competitive post-layout metrics compared to state-of-the-art BO methods and notably improved early-stage exploration and uncertainty quantification, particularly under limited observations. The approach offers a path toward more efficient, context-aware exploration of analog design spaces, with open-source code to facilitate adoption and further development.
Abstract
Analog layout synthesis faces significant challenges due to its dependence on manual processes, considerable time requirements, and performance instability. Current Bayesian Optimization (BO)-based techniques for analog layout synthesis, despite their potential for automation, suffer from slow convergence and extensive data needs, limiting their practical application. This paper presents the \texttt{LLANA} framework, a novel approach that leverages Large Language Models (LLMs) to enhance BO by exploiting the few-shot learning abilities of LLMs for more efficient generation of analog design-dependent parameter constraints. Experimental results demonstrate that \texttt{LLANA} not only achieves performance comparable to state-of-the-art (SOTA) BO methods but also enables a more effective exploration of the analog circuit design space, thanks to LLM's superior contextual understanding and learning efficiency. The code is available at https://github.com/dekura/LLANA.