A 2.5-nA Area-Efficient Temperature-Independent 176-/82-ppm/°C CMOS-Only Current Reference in 0.11-$μ$m Bulk and 22-nm FD-SOI

TL;DR

A nA-range constant-with-temperature (CWT) current reference is introduced, relying on a self-cascode MOSFET biased by a four-transistor ultra-low-power voltage reference through a single-transistor buffer through a single-transistor buffer to maintain performance across process corners.

Abstract

Internet-of-Things (IoT) applications require nW-power current references that are robust to process, voltage and temperature (PVT) variations, to maintain the performance of IoT sensor nodes in a wide range of operating conditions. However, nA-range current references are rarely area-efficient due to the use of large gate-leakage transistors or resistors, which occupy a significant silicon area at this current level. In this paper, we introduce a nA-range constant-with-temperature (CWT) current reference, relying on a self-cascode MOSFET (SCM) biased by a four-transistor ultra-low-power voltage reference through a single-transistor buffer. The proposed reference includes a temperature coefficient (TC) calibration mechanism to maintain performance across process corners. In addition, as the proposed design relies on the body effect, it has been fabricated and measured in 0.11-$μ$m bulk and 22-nm fully-depleted silicon-on-insulator (FD-SOI) to demonstrate feasibility in both technology types. On the one hand, the 0.11-$μ$m design consumes a power of 16.8 nW at 1.2 V and achieves a 2.3-nA current with a line sensitivity (LS) of 2.23 %/V at 25°C and a TC of 176 ppm/°C at 1.2 V from -40 to 85°C. On the other hand, the 22-nm design consumes a power of 16.3 nW at 1.5 V and achieves a 2.5-nA current with a 1.53-%/V LS at 25°C and an 82-ppm/°C TC at 1.5 V from -40 to 85°C. Thanks to their simple architecture, the proposed references achieve a silicon area of 0.0106 mm$^2$ in 0.11 $μ$m and 0.0026 mm$^2$ in 22 nm without compromising other figures of merit, and are thus competitive with state-of-the-art CWT references operating in the same current range.

Figures (26)

• Figure 1: The area efficiency of nA-range CWT current references can be improved by using an SCM as $\boldsymbol{V}$-to-$\boldsymbol{I}$ converter, and by simplifying the $\boldsymbol{V_{REF}}$ generation and buffering. (a) Tradeoff between silicon area and reference current, featuring the scarcity of measured area-efficient solutions in the nA range. (b) Conventional CWT current references are based on a reference voltage applied to a $V$-to-$I$ converter, which can either be (c) a gate-leakage transistor, an SCM, or a resistor, respectively well suited to the generation of pA-, nA-, or $\mu$A-range reference current. (d) Voltage reference implemented with a 2T structure and a 1T buffer Wang_2018Lefebvre_2022.
• Figure 2: (a) Basic schematic of the proposed current reference, which consists of (b) an SCM ($M_{1-2}$) biased by a pMOS current mirror ($M_{3-4}$), and (c) a 4T voltage reference ($M_{6-9}$) generating a PTAT voltage with a CWT offset, biasing the SCM through a 1T buffer ($M_5$).
• Figure 3: Operation principle of PTAT references proposed in prior art CamachoGaleano_2005CamachoGaleano_2008 (in orange) and of the proposed CWT reference (in blue). Analytical expression of (a) the voltage $V_X$ applied to the SCM, (b) the inversion level of $M_2$, denoted as $i_{f2}$, and (c) the reference current $I_{REF}$, as a function of temperature and for $V_{off}$ = 20 mV. Generic technological parameters $n$ = 1.2 and $m$ = 1.5 are selected. (b) and (c) are normalized to their value at 25$^\circ$C. For the proposed CWT reference, the parameters leading to a minimum $I_{REF}$ TC are $K_{PTAT} = 8$ and $\alpha = 1.5$.
• Figure 4: All figures correspond to generic technological parameters $n$ = 1.2, $\gamma_b^{*}$ = 0.15, and $V_{BS7}$ = 0.2 V, and rely on a body effect model corresponding to an FD-SOI technology. Temperature dependence of $V_X$ for (a) a sweep of $S_7$ and a fixed $S_9/S_6$ = 8, and (d) a sweep of $S_9$ and a fixed $S_7/S_6$ = 2. (b) $V_X$ CWT offset for the $S_7$ sweep in (a), and (c) $V_X$ PTAT slope for the sweeps shown in (a) and (d), estimated as the variations of $V_X$ across the temperature range divided by the temperature range.
• Figure 5: Four-step flowchart of the design and sizing methodology.