Logic Synthesis with Generative Deep Neural Networks

TL;DR

This paper tackles the challenge of applying deep learning to logic synthesis under strict equivalence constraints. It introduces ctrw, a rewriting operator built on the Circuit Transformer that preserves equivalence during subgraph replacement. A two-stage training regime—supervised pretraining plus iterative self-improvement via Monte-Carlo Tree Search—together with DAG-aware and fanout-free window rewriting enables scalable, equivalence-preserving optimization. Experiments on the IWLS 2023 benchmark show substantial circuit-size reductions and feasibility guarantees, indicating a viable path for neural-guided logic synthesis on larger circuits via AI platforms.

Abstract

While deep learning has achieved significant success in various domains, its application to logic circuit design has been limited due to complex constraints and strict feasibility requirement. However, a recent generative deep neural model, "Circuit Transformer", has shown promise in this area by enabling equivalence-preserving circuit transformation on a small scale. In this paper, we introduce a logic synthesis rewriting operator based on the Circuit Transformer model, named "ctrw" (Circuit Transformer Rewriting), which incorporates the following techniques: (1) a two-stage training scheme for the Circuit Transformer tailored for logic synthesis, with iterative improvement of optimality through self-improvement training; (2) integration of the Circuit Transformer with state-of-the-art rewriting techniques to address scalability issues, allowing for guided DAG-aware rewriting. Experimental results on the IWLS 2023 contest benchmark demonstrate the effectiveness of our proposed rewriting methods.

Figures (4)

• Figure 1: The pipeline of Circuit Transformer that transforms a circuit to a strictly equivalent one.
• Figure 2: The process of Iterative Self-Improvement Training. Two stages are included in a single iteration: (1) Training: the Circuit Transformer is supervisedly fine-tuned by circuit pairs $<G_{t-1}, G'_{t-1}>$, with its weight updated from $\theta_{t-1}$ to $\theta_t$; (2) Improvement: a batch of raw circuits $G_t$ is sampled from the full dataset, and processed by MCTS-enhanced Circuit Transformer with weight $\theta_t$ to generate further optimized circuits $G'_t$.
• Figure 3: An example showing how a sub-circuit can be replaced by a non-equivalent one, without changing the functionality of the whole circuit.
• Figure 4: Examples showing how the reward is refined in the sequential generation process, so that the cumulative reward correctly reflects the total number of added AND nodes.