Stochastic logic in biased coupled photonic probabilistic bits

Abstract

Optical computing often employs tailor-made hardware to implement specific algorithms, trading generality for improved performance in key aspects like speed and power efficiency. An important computing approach that is still missing its corresponding optical hardware is probabilistic computing, used e.g. for solving difficult combinatorial optimization problems. In this study, we propose an experimentally viable photonic approach to solve arbitrary probabilistic computing problems. Our method relies on the insight that coherent Ising machines composed of coupled and biased optical parametric oscillators can emulate stochastic logic. We demonstrate the feasibility of our approach by using numerical simulations equivalent to the full density matrix formulation of coupled optical parametric oscillators.

Figures (4)

• Figure 1: Illustration of the three-step conversion process. We take the truth table from a (basic) digital logic gate and map it to a network of $p$-bits. This amounts to describing the gate as an Ising model with a coupling term ($J$) and a local magnetic field ($\vec{h}$). We then find the ground state of the Ising model by looking at the steady state of a network of (i.e. coupled) optical parametric oscillators (OPOs) that are biased by an injected field.
• Figure 2: Fundamental p-gates implemented with a biased coupled OPO network. (a) Truth table of the AND-gate. (b) Corresponding Ising Hamiltonian with three spins. (c) All possible spin configurations of the Hamiltonian depicted in (b) with their corresponding energy $E$. The ground states reproduce the correct logic from the truth table. (d)-(e) We plot the probability for each possible spin configuration of the three (AND), four (HA), and five (FA) spins as a function of the number of cavity round-trips. Depicted is the probability that the OPO network is currently in a ground state of the corresponding Ising Hamiltonian (green), and in an excited state (dark orange, dashed).
• Figure 3: Solving the semiprime factorization problem with a coupled and biased network of OPOs. (a) Digital logic circuit that multiplies two 3-bit numbers ($X$ and $Y$ in their binary representations, respectively), resulting in $Z$ (binary representation). The lines interconnecting the gates are represented by auxiliary spins in the Ising Hamiltonian. The inset shows the corresponding Ising Hamiltonian with coupling $J$ at the top and Zeeman term $\vec{h}$ at the bottom. (b) Time evolution of the in-phase component ($c_i$) of coupled and biased OPOs with $J$ and $\vec{h}$ originating from the 6-bit multiplier circuit. The steady state of this configuration represents the ground state of the Ising Hamiltonian, solving the factorization problem.
• Figure 4: Solving the Boolean satisfiability ($\text{SAT}$) problem. (a) The digital logic circuit of one clause in the $3\text{SAT}$ problem is shown with the corresponding Ising Hamiltonian. (b) Temporal evolution towards the steady state of the in-phase component ($c$, blue lines) of 384 coupled and biased OPOs with $J$ and $\vec{h}$ originating from the $3\text{SAT}$ problem with 20 variables and 91 clauses. From the steady state, we can read off one solution to the $3\text{SAT}$ problem. The orange line plots the evolution of the percentage of clauses satisfied.