The Logarithmic Memristor-Based Bayesian Machine

TL;DR

The logarithmic memristor-based Bayesian machine is introduced, an innovative design that leverages the unique properties of memristors and logarithmic computing as an alternative to stochastic computing and enables the development of energy-efficient and reliable AI systems for edge devices.

Abstract

The demand for explainable and energy-efficient artificial intelligence (AI) systems for edge computing has led to significant interest in electronic systems dedicated to Bayesian inference. Traditional designs of such systems often rely on stochastic computing, which offers high energy efficiency but suffers from latency issues and struggles with low-probability values. In this paper, we introduce the logarithmic memristor-based Bayesian machine, an innovative design that leverages the unique properties of memristors and logarithmic computing as an alternative to stochastic computing. We present a prototype machine fabricated in a hybrid CMOS/hafnium-oxide memristor process. We validate the versatility and robustness of our system through experimental validation and extensive simulations in two distinct applications: gesture recognition and sleep stage classification. The logarithmic approach simplifies the computational model by converting multiplications into additions and enhances the handling of low-probability events, which are crucial in time-dependent tasks. Our results demonstrate that the logarithmic Bayesian machine achieves superior performance in terms of accuracy and energy efficiency compared to its stochastic counterpart, particularly in scenarios involving complex probabilistic models. This work paves the way for the deployment of advanced AI capabilities in edge devices, where power efficiency and reliability are paramount.

Figures (4)

• Figure 1: General architecture of the logarithmic Bayesian machine.a Optical microscopy image of the die of the fabricated machine. b Electron microscopy image of a memristor integrated in the CMOS backend of line of our process. c Photograph of the logarithmic Bayesian machine test setup. d Simplified schematic of the implemented logarithmic Bayesian machine. All log-probabilities are coded as eight-bit integers, following eq. \ref{['eq:entier']}.
• Figure 2: Experimental implementation of sleep stage classification throughout the night.a Inputs and and outputs of the logarithmic Bayesian machine used for sleep stage classification. b Bayesian network model implemented on the logarithmic Bayesian machine used for sleep stage classification. c Experimentally measured test accuracy of the logarithmic Bayesian machine, averaged over 1000 five-second segments. The measurement was repeated for various supply voltages VDD.
• Figure 3: Benchmarking the accuracy and the energy consumption of the stochastic and logarithmic Bayesian machines.a,b Accuracy of the stochastic machine on a gesture recognition and b sleep stage classification, as a function of number of clock cycles, using the conventional stochastic computing or the power conscious approach. The accuracy of the logarithmic machine (one clock cycle) is plotted as a reference. Error bars are defined in the Methods section. c,d Energy consumption as a function of accuracy for c gesture recognition and d sleep stage classification, using all approaches considered in a,b. This Figure is obtained associating several simulation methodologies (see Methods).
• Figure 4: Resilience of the stochastic and logarithmic Bayesian machine to memristor bit error rate. Accuracy of the stochastic (using conventional and power-conscious computation) and logarithmic Bayesian machines as a function of the memristor bit error rates, for a gesture recognition and b sleep stage classification tasks. This Figure is obtained using Monte Carlo simulation (see Methods). Error bars/shadows represent one standard deviation when repeating the simulation with different memory errors. Stochastic computing simulations in a use 100 cycles, and in b 4096 cycles.