Floorplanning with I/O assignment via feasibility-seeking and superiorization methods

TL;DR

This work reframes floorplanning as a feasibility-seeking problem (FSP) using a union of convex constraint sets and introduces a perturbed, resettable MAP variant (Per-RMAP) guided by the superiorization method to jointly achieve feasibility and reduced $HPWL$. Theoretical results establish local convergence properties for MAP under union-convex constraints and illustrate oscillation phenomena that motivate resetting strategies. Empirically, Per-RMAP delivers substantial speedups (up to $166\times$) over branch-and-bound with modest wirelength penalties (about $5\%$), and IO-assignment and soft-module variants yield additional wirelength and runtime gains. Overall, the approach demonstrates a scalable, efficient pathway for floorplanning under heterogeneous constraints with practical impact for large-scale IC designs.

Abstract

The feasibility-seeking approach offers a systematic framework for managing and resolving intricate constraints in continuous problems, making it a promising avenue to explore in the context of floorplanning problems with increasingly heterogeneous constraints. The classic legality constraints can be expressed as the union of convex sets. In implementation, we introduce a resetting strategy aimed at effectively reducing the problem of algorithmic divergence in the projection-based method used for the feasibility-seeking formulation. Furthermore, we introduce the novel application of the superiorization method (SM) to floorplanning, which bridges the gap between feasibility-seeking and constrained optimization. The SM employs perturbations to steer the iterations of the feasibility-seeking algorithm towards feasible solutions with reduced (not necessarily minimal) total wirelength. To evaluate the performance of Per-RMAP, we conduct comprehensive experiments on the MCNC benchmarks and GSRC benchmarks. The results demonstrate that we can obtain legal floorplanning results 166 times faster than the branch-and-bound (B&B) method while incurring only a 5% wirelength increase compared to the optimal results. Furthermore, we evaluate the effectiveness of the algorithmic flow that considers the I/O assignment constraints, which achieves an 6% improvement in wirelength. Besides, considering the soft modules with a larger feasible solution space, we obtain 15% improved runtime compared with PeF, the state-of-the-art analytical method. Moreover, we compared our method with Parquet-4 and Fast-SA on GSRC benchmarks which include larger-scale instances. The results highlight the ability of our approach to maintain a balance between floorplanning quality and efficiency.

Figures (12)

• Figure 1: Illustration of $d_{esc}(z^*,C_t)$ and $d_{sep}(z^*,C_t)$ when $t=\left(i,j\right)$, where the black point is the point $z^*$. Here, $K_t(z^*)=\left\{\mathsf{L}\right\}$, corresponding to the indice of the dark green region.
• Figure 2: Oscillation for n4 occurs for bad initialization.
• Figure 3: Case 1: begin at the LHS case of Fig. \ref{['fig:4-cell-oscillation']}, finish at the RHS case of Fig. \ref{['fig:4-cell-oscillation']} after applying a sweep of MAP.
• Figure 4: Case 2: begin and finish at the LHS case of Fig. \ref{['fig:4-cell-oscillation']} after applying a sweep of MAP.
• Figure 5: Algorithmic flow

Theorems & Definitions (24)

• Definition 1: Fixed Point Set
• Definition 2: Lyapunov stability
• Lemma 1
• proof
• Definition 3: Active Indices
• Definition 4: Escaping Distance from Active Indices
• Definition 5: Separating Distance to Non-active Indices
• Lemma 2
• proof
• Definition 6: Sequential MAP Trajectory