The computational power of random quantum circuits in arbitrary geometries

TL;DR

The paper investigates the boundary between classical and quantum computational power by sampling outputs from highly connected random quantum circuits implemented on Quantinuum's H2 trapped-ion processor. It combines exact tensor-network contraction costs, memory-constrained slicing, and approximate TN methods to model classical hardness across random-geometry and 2D circuit geometries. With H2 upgraded to 56 qubits and near-unity 2Q gate fidelity, the work demonstrates sampling from classically challenging circuits at scales that stress state-of-the-art classical algorithms, while providing bounds and models that clarify when classical simulations remain feasible. The results illuminate how circuit connectivity and hardware fidelity interplay to sustain quantum advantage, offering a roadmap for scaling RCS demonstrations on QCCD architectures and guiding future hardware improvements.

Abstract

Empirical evidence for a gap between the computational powers of classical and quantum computers has been provided by experiments that sample the output distributions of two-dimensional quantum circuits. Many attempts to close this gap have utilized classical simulations based on tensor network techniques, and their limitations shed light on the improvements to quantum hardware required to frustrate classical simulability. In particular, quantum computers having in excess of $\sim 50$ qubits are primarily vulnerable to classical simulation due to restrictions on their gate fidelity and their connectivity, the latter determining how many gates are required (and therefore how much infidelity is suffered) in generating highly-entangled states. Here, we describe recent hardware upgrades to Quantinuum's H2 quantum computer enabling it to operate on up to $56$ qubits with arbitrary connectivity and $99.843(5)\%$ two-qubit gate fidelity. Utilizing the flexible connectivity of H2, we present data from random circuit sampling in highly connected geometries, doing so at unprecedented fidelities and a scale that appears to be beyond the capabilities of state-of-the-art classical algorithms. The considerable difficulty of classically simulating H2 is likely limited only by qubit number, demonstrating the promise and scalability of the QCCD architecture as continued progress is made towards building larger machines.

Figures (35)

• Figure 1: Demonstration of how a densely-gated circuit ($N/2$ 2Q gates per layer) with arbitrary connectivity is executed on the H2 quantum computer. (a) The first layer is executed by assigning each qubit to a unique $^{171}{\rm Yb}^{+}$ ion (colored disk) such that gated qubits are co-located; each ion is labeled by a unique color, and the black lines connecting neighbors indicate that the associated qubits will be gated. Since H2 is currently configured with 4 active gate zones, the two-qubit (2Q) gates are executed in 7 batches of 4 parallel gates. (b) The first batch of four gates [highlighted in magenta in (a)] are executed in parallel in the bottom row of gate zones, and qubits are then shuffled around the trap in a "rolodex" fashion until all gates (including 1Q gates) in the first layer have been applied. (c) The next layer of gates can act on arbitrary pairs. (d) An automated compilation step decides where to locate qubits in the trap (placement) and how to get them there (routing), resulting in a new assignment of qubit positions that ensures all pairs of qubits to be gated in this layer are once again co-located. Given the placement determined in (d), sequences of voltages are applied to the trap electrodes that, via a combination of the split/combine, shift, and swap operations shown in (e) achieve the desired ion placement for this layer of gates shown in (f). The gates can once again be executed in a rolodex fashion, and this entire process is repeated until all layers of gates have been applied. Note that additional coolant ions are omitted in these illustrations; as described in Ref. Pino2020moses2023race each $^{171}{\rm Yb}^{+}$ qubit ion is paired with a $^{138}{\rm Ba}^{+}$ coolant ion.
• Figure 2: The circuits considered in this paper have geometries induced by random regular graphs. For a depth-$d$ circuit on $N$ qubits, denoted $C_{d,N}$, we sample a random $d$-regular graph on $N$ nodes, denoted $\mathcal{G}_{d,N}$ (the example shown above is for a depth-3 circuit on 6 qubits). To arrive at a circuit we associate each vertex of $\mathcal{G}$ with a qubit in $C$, and then assign $\mathcal{G}$ an edge-coloring. Each color is associated with a layer of 2Q gates in $C$, with each edge of that color corresponding to a 2Q gate in that layer. Adjacent 2Q layers are separated by a layer of Haar-random 1Q gates on each qubit (with a single layer of 1Q gates immediately after state preparation and another immediately before measurement).
• Figure 3: Comparison of complexity density $\mathscr{C}_{d,N}$ for circuits with random geometries (RG) and 2D geometries. Figures (a) and (b) show the gating pattern for a depth-4 graph on $56$ qubits given random and 2D geometries, respectively. At each value $(N,d)$, an $N$-node graph is assigned a coloring using either $d$ colors (RG) or $4$ colors (2D). Each circuit is comprised of layers of $U_{\rm ZZ}(\pi/2)$ gates separated by layers of random $SU(2)$ gates on each qubit, with the $U_{\rm ZZ}$ gates applied to each pair of qubits whose associated vertices are joined by an edge of one color. In (a) each layer corresponds to a unique color, while in (b) the $4$ colors are repeated cyclically until the desired depth is reached. Figures (c) and (d) show estimates of $\mathscr{C}_{d,N}$ for such RG and 2D circuits, respectively. While the complexity density for RG circuits is constant for $N\rightarrow\infty$ at fixed depth [evidenced by the horizontal contours in (c)], the log-log plot in the inset of (d) shows that $d\sim \sqrt{N}$ is required to maintain fixed complexity density in 2D. The white arrows in (c,d) highlight how far the depth needs to be increased at $N=56$ before the complexity density saturates (i.e. the TN contraction cost becomes roughly equivalent to the cost of doing brute-force $N=56$ state vector simulation).
• Figure 4: The impact of constraining memory on cost for TN contraction of a single amplitude for random quantum circuits with $N=56$. (a) FLOP cost of unconstrained optimized contraction paths compared with those sliced to $W{=}2^{30}$ as a function of circuit depth, $d$. The cost of statevector simulation is marked for reference. (b) Size of the largest intermediate tensor, or 'contraction width', $W$, as a function of circuit depth. The lines represent the median behavior across 20 circuit instances, with the bands showing the min/max range.
• Figure 5: (a) Achievable error per gate $\varepsilon_{\rm MPS}$ as a function of circuit depth using DMRG for circuits with 2D and random geometries and a variety of 1Q and 2Q gate sets. All curves use a bond dimension $\chi=256$, and shaded regions show standard deviation of the error per gate across 100 (20) circuit randomizations for random (2D) circuits. (b) Error per gate at depth 20 as a function of bond dimension. Linear extrapolation of $\varepsilon_{\rm MPS}$ to the experimental value of $\varepsilon \approx 3.2\times 10^{-3}$ (dotted horizontal line in this figure, see Sec. \ref{['sec:exp_results']}) from the two largest bond dimensions suggests that by depth $20$, DMRG cannot simulate random geometry circuits at the fidelities achieved on $H2$ without employing an essentially exact representation of the full statevector (MPS bond-dimension $\chi=2^{N/2=28}$, green vertical line).