Resource Optimized Quantum Squaring Circuit

TL;DR

The paper introduces a garbageless quantum squaring circuit (QSC) optimized for fault-tolerant Clifford + $T$ gates, achieving substantial reductions in $T$-count, $T$-depth, $CNOT$-count, $CNOT$-depth, and $KQ_T$ compared to prior designs. It achieves these gains by a novel arrangement of partial products that halves the number of adders and by employing the resource-efficient logical-AND gate and its uncomputation from Gidney et al. The approach yields asymptotic improvements (e.g., $66.67\%$ lower $T$-count vs Thapliyal et al. and $77.27\%$ vs Nagamani et al.) while maintaining a qubit cost of the same $O(n^{2})$ order, making the QSC a strong candidate as a building block for quantum linear algebra, cryptography, and related numerical algorithms. The work provides detailed cost analyses across parity cases and positions the QSC as a practical, garbage-free alternative for fault-tolerant quantum arithmetic.

Abstract

Quantum squaring operation is a useful building block in implementing quantum algorithms such as linear regression, regularized least squares algorithm, order-finding algorithm, quantum search algorithm, Newton Raphson division, Euclidean distance calculation, cryptography, and in finding roots and reciprocals. Quantum circuits could be made fault-tolerant by using error correcting codes and fault-tolerant quantum gates (such as the Clifford + T-gates). However, the T-gate is very costly to implement. Two qubit gates (such as the CNOT-gate) are more prone to noise errors than single qubit gates. Consequently, in order to realize reliable quantum algorithms, the quantum circuits should have a low T-count and CNOT-count. In this paper, we present a novel quantum integer squaring architecture optimized for T-count, CNOT-count, T-depth, CNOT-depth, and $KQ_T$ that produces no garbage outputs. To reduce costs, we use a novel approach for arranging the generated partial products that allows us to reduce the number of adders by 50%. We also use the resource efficient logical-AND gate and uncomputation gate shown in [1] to further save resources. The proposed quantum squaring circuit sees an asymptotic reduction of 66.67% in T-count, 50% in T-depth, 29.41% in CNOT-count, 42.86% in CNOT-depth, and 25% in KQ T with respect to Thapliyal et al. [2]. With respect to Nagamani et al. [3] the design sees an asymptotic reduction of 77.27% in T-count, 68.75% in T-depth, 50% in CNOT-count, 61.90% in CNOT-depth, and 6.25% in the $KQ_T$.

Figures (7)

• Figure 1: The logical-AND gate and its Clifford + T-gate implementation C.Gidney.et.al-2018
• Figure 3: Step 1: Generation of Partial Products from logical-AND gate for 6-bit input number $a$. Here, the value $|a\textsubscript{0}\rangle$ is the least significant bit $|P\textsubscript{0}\rangle$ of the squared value of the input $a$.
• Figure 4: Step 2: The arranged partial products along with ancillae is placed at a quantum register $|T\rangle$ for 6-bit input number $a$ is shown above. For example, the generated partial product $|a\textsubscript{0}a\textsubscript{1}\rangle$ is placed at quantum register location $|T\textsubscript{1,0}\rangle$, $|$a0a1$\rightarrow$T1,0$\rangle$.
• Figure 5: Step 3: The remaining array of generated partial products from step 2 are zero padded and placed to a quantum register $|T\rangle$ for 6-bit input number $a$. For example, $|a\textsubscript{1}a\textsubscript{2}\rangle$ value is put at quantum register location value $|T\textsubscript{2,0}\rangle$, $|$a1a2$\rightarrow$T2,0$\rangle$.
• Figure 6: Step 4: The arranged partial products of 6-bit input number $a$ obtained from logical-ANDs are input to $2n-3$ bit adder. The sum values $|S\rangle$ are the outputs from the adder. $|P\rangle$ values are the squared qubits of input $a$. The value of $|P\textsubscript{1}\rangle$ of the squared qubits ($a^{2}$) of input $a$ is from ancillae $|0\rangle$. The sum bits $|S\textsubscript{0}\rangle$, $|S\textsubscript{1}\rangle$ are bits $|P\textsubscript{2}\rangle$$|P\textsubscript{3}\rangle$ of the squared value $|a\textsubscript{2}\rangle$. Along with the sum bits the input $|T\textsubscript{0,0}\rangle$ to $|T\textsubscript{0,8}\rangle$ are regenerated for 6-bit input number $a$.