High Throughput Polar Code Decoders with Information Bottleneck Quantization

TL;DR

The paper tackles the high hardware cost of polar code decoders by employing Information Bottleneck-based non-uniform quantization within optimized Fast-SSC architectures. It develops fully unrolled, deeply pipelined IB-enabled decoders implemented in 12 nm FinFET and demonstrates significant area and energy efficiency gains at high throughput and stringent FER targets. Key contributions include seven designs for Polar$(128,64)$ and Polar$(1024,512)$, LUT-based reconstruction to manage non-uniform quantization, and detailed hardware-performance comparisons showing up to ~16% area and ~13% energy efficiency gains. The work validates that non-uniform IB quantization can preserve decoding performance while reducing memory and logic requirements, offering practical benefits for high-throughput FEC in next-generation wireless standards.

Abstract

In digital baseband processing, the forward error correction (FEC) unit belongs to the most demanding components in terms of computational complexity and power consumption. Hence, efficient implementation of FEC decoders is crucial for next generation mobile broadband standards and an ongoing research topic. Quantization has a significant impact on the decoder area, power consumption and throughput. Thus, lower bit-widths are preferred for efficient implementations but degrade the error-correction capability. To address this issue, a non-uniform quantization based on the Information Bottleneck (IB) method was proposed that enables a low bit width while maintaining the essential information. Many investigations on the use of IB method for Low-density parity-check code (LDPC) decoders exist and have shown its advantages from an implementation perspective. However, for polar code decoder implementations, there exists only one publication that is not based on the state-of-the-art Fast-SSC decoding algorithm, and only synthesis implementation results without energy estimation are shown. In contrast, our paper presents several optimized Fast Simplified Successive-Cancellation (Fast-SSC) polar code decoder implementations using IB-based quantization with placement&routing results in an advanced 12 nm FinFET technology. Gains of up to 16% in area and 13% in energy efficiency are achieved with IB-based quantization at a Frame Error Rate (FER) of 10-7 and a Polar Code of N = 1024, R = 0.5 compared to state-of-the-art decoders.

Figures (5)

• Figure 1: schematic for the $g$-function
• Figure 2: Unrolled and pipelined Fast-SSC decoder architecture for a $\mathcal{P}(16,8)$. Colors represent numerical domains: green for IB, red for FP, blue for binary and dark green shows the LUTs.
• Figure 3: of the $\mathcal{P}(128,64)$, Float vs. FP vs. IB Quantization
• Figure 4: of the $\mathcal{P}(1024,512)$, Float vs. vs.
• Figure 5: Layout pictures for FP and IB polar code decoders