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A time-to-digital converter with steady calibration through single-photon detection

Matías Rubén Bolaños Wagner, Daniele Vogrig, Paolo Villoresi, Giuseppe Vallone, Andrea Stanco

TL;DR

The paper addresses the need for reliable, high-precision time stamping in FPGA-based TDCs for quantum communications by introducing MARTY, a steady-calibration TDC that uses single-photon detection to calibrate on-the-fly without stopping data acquisition. The architecture combines a 48-bit coarse counter at $τ_{coarse}=1/f_s ≈ 2.42$ ns with a fine-delay line of 144 fast-carry elements, achieving a calibrated resolution of $τ_{res} = 18.22$ ps and jitter of $τ_{jitter} = 27.11$ ps. Key findings include robust steady calibration across $5$ °C to $80$ °C (⟨σ_{steady}⟩ = 0.64 ps), the ability to stream up to ~12–15 Mevents/s for about a week without overflow, and QKD performance with QBER ≈ 2.2% comparable to a commercial time-tagger (QuTAG). The work demonstrates substantial practical impact for satellite and terrestrial QKD, enabling continuous, accurate time tagging without data loss, and outlines paths toward higher performance FPGA platforms like Ultrascale+.

Abstract

Time-to-Digital Converters (TDCs) are a crucial tool in a wide array of fields, in particular for quantum communication, where time taggers performance can severely affect the quality of the entire application. Nowadays, FPGA-based TDCs present a viable alternative to ASIC ones, once the nonlinear behaviour due to the intrinsic nature of the device is properly mitigated. To compensate said nonlinearities, a calibration procedure is required, usually based on an interpolation methods. Here we present the design and the demonstration of a TDC that is FPGA-based and showing a residual jitter of 27 ps, that is scalable for multichannel operation. The application in Quantum Key Distribution (QKD) is discussed with a unique calibration method based on the exploitation of single-photon detection that does not require to stop the data acquisition or to use any interpolation methods, thus increasing accuracy and removing data loss. The calibration was tested in a relevant environment, investigating the device behaviour between 5°C and 80°C. Moreover, our design is capable of continuously streaming up to 12 Mevents/s for up to ~1 week without the TDC overflowing.

A time-to-digital converter with steady calibration through single-photon detection

TL;DR

The paper addresses the need for reliable, high-precision time stamping in FPGA-based TDCs for quantum communications by introducing MARTY, a steady-calibration TDC that uses single-photon detection to calibrate on-the-fly without stopping data acquisition. The architecture combines a 48-bit coarse counter at ns with a fine-delay line of 144 fast-carry elements, achieving a calibrated resolution of ps and jitter of ps. Key findings include robust steady calibration across °C to °C (⟨σ_{steady}⟩ = 0.64 ps), the ability to stream up to ~12–15 Mevents/s for about a week without overflow, and QKD performance with QBER ≈ 2.2% comparable to a commercial time-tagger (QuTAG). The work demonstrates substantial practical impact for satellite and terrestrial QKD, enabling continuous, accurate time tagging without data loss, and outlines paths toward higher performance FPGA platforms like Ultrascale+.

Abstract

Time-to-Digital Converters (TDCs) are a crucial tool in a wide array of fields, in particular for quantum communication, where time taggers performance can severely affect the quality of the entire application. Nowadays, FPGA-based TDCs present a viable alternative to ASIC ones, once the nonlinear behaviour due to the intrinsic nature of the device is properly mitigated. To compensate said nonlinearities, a calibration procedure is required, usually based on an interpolation methods. Here we present the design and the demonstration of a TDC that is FPGA-based and showing a residual jitter of 27 ps, that is scalable for multichannel operation. The application in Quantum Key Distribution (QKD) is discussed with a unique calibration method based on the exploitation of single-photon detection that does not require to stop the data acquisition or to use any interpolation methods, thus increasing accuracy and removing data loss. The calibration was tested in a relevant environment, investigating the device behaviour between 5°C and 80°C. Moreover, our design is capable of continuously streaming up to 12 Mevents/s for up to ~1 week without the TDC overflowing.
Paper Structure (8 sections, 6 equations, 8 figures)

This paper contains 8 sections, 6 equations, 8 figures.

Table of Contents

  1. Introduction
  2. Materials and methods
  3. Design of the device
  4. System calibration and auto-calibration
  5. Temperature test setup
  6. Quantum Key Distribution test setup
  7. Results and discussions
  8. Conclusion

Figures (8)

  • Figure 1: Functioning principle of a steadily-calibrated TDC (right) compared with a normal TDC (left).
  • Figure 2: (a) Histogram obtained with a code density test using an FPGA-based RO as input. (b) Percentile difference of the histogram obtained with a code density test using a laser detection signal with respect to the RO one.
  • Figure 3: $\text{DNL}$ (in blue) and $\text{DNL}^{t}$ (in red) obtained for a single channel of the TDC at room temperature.
  • Figure 4: Calibrated time as a function of the bin number of the TDC, in orange the ideal behaviour for a uniform delay line.
  • Figure 5: Histogram of the difference between two consecutive timetags in a two-channel implementation. In red, the corresponding Gaussian fit, from which the jitter was estimated.
  • ...and 3 more figures