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SCALLER: Standard Cell Assembled and Local Layout Effect-based Ring Oscillators

Muayad J. Aljafar, Zain Ul Abideen, Adriaan Peetermans, Benedikt Gierlichs, Samuel Pagliarini

TL;DR

Process variation limits ring oscillator frequency control, and the paper introduces a digital, standard-cell–based tunable RO design that exploits the Well Proximity Effect (WPE) as a local layout effect. The approach builds 9-stage ROs with tunable stages controlled by a MUX and pairs LLE-based ROs with reference ROs to decouple local from global variations. Post-silicon measurements across 100 chips show finetuned frequency control, achieving tunability up to about $8$ MHz with a typical step of $90$ kHz, across multiple configurations (5/6/7 MUX). This method is compatible with on-chip PLLs and TRNGs, offering robust, area-efficient, all-digital tunability for high-performance clocking and random-number generation.

Abstract

This letter presents a technique that enables very fine tunability of the frequency of Ring Oscillators (ROs). Multiple ROs with different numbers of tunable elements were designed and fabricated in a 65nm CMOS technology. A tunable element consists of two inverters under different local layout effects (LLEs) and a multiplexer. LLEs impact the transient response of inverters deterministically and allow to establish a fine tunable mechanism even in the presence of large process variation. The entire RO is digital and its layout is standard-cell compatible. We demonstrate the tunability of multi-stage ROs with post-silicon measurements of oscillation frequencies in the range of 80-900MHz and tuning steps of 90KHz

SCALLER: Standard Cell Assembled and Local Layout Effect-based Ring Oscillators

TL;DR

Process variation limits ring oscillator frequency control, and the paper introduces a digital, standard-cell–based tunable RO design that exploits the Well Proximity Effect (WPE) as a local layout effect. The approach builds 9-stage ROs with tunable stages controlled by a MUX and pairs LLE-based ROs with reference ROs to decouple local from global variations. Post-silicon measurements across 100 chips show finetuned frequency control, achieving tunability up to about MHz with a typical step of kHz, across multiple configurations (5/6/7 MUX). This method is compatible with on-chip PLLs and TRNGs, offering robust, area-efficient, all-digital tunability for high-performance clocking and random-number generation.

Abstract

This letter presents a technique that enables very fine tunability of the frequency of Ring Oscillators (ROs). Multiple ROs with different numbers of tunable elements were designed and fabricated in a 65nm CMOS technology. A tunable element consists of two inverters under different local layout effects (LLEs) and a multiplexer. LLEs impact the transient response of inverters deterministically and allow to establish a fine tunable mechanism even in the presence of large process variation. The entire RO is digital and its layout is standard-cell compatible. We demonstrate the tunability of multi-stage ROs with post-silicon measurements of oscillation frequencies in the range of 80-900MHz and tuning steps of 90KHz
Paper Structure (8 sections, 8 figures, 2 tables)

This paper contains 8 sections, 8 figures, 2 tables.

Table of Contents

  1. Introduction
  2. Background and Proposed Approach
  3. Well Proximity Effect (WPE)
  4. Tunable ROs
  5. Chip Design and Measurements
  6. Power Analysis
  7. Impact of WPE on Tunability
  8. Conclusions

Figures (8)

  • Figure 1: Well Proximity Effect. Three simplified transistor layouts with different values of X are shown.
  • Figure 2: Transient response of three inverters with baseline and manipulated PMOS transistors. Obtained from electrical simulation in Cadence Spectre.
  • Figure 3: Structure of the proposed tunable stage (TS). Multiple configurations for building an RO were considered. All ROs have 9 stages, 8 from inverters and one from a NAND gate.
  • Figure 4: Layout of 5MUX RO pair ($24.9 \mu m\times 10.8\mu m)$ that is compatible with std. cell row-based design. The highlighted TS consists of a MUX (middle) with two manipulated inverters (above and below). Well sizes are normalized.
  • Figure 5: Layout ($960\mu m \times 960\mu m$) and die micrograph. Colorful rectangles in the layout view are the pairs of ROs.
  • ...and 3 more figures