A 0.96pJ/SOP, 30.23K-neuron/mm^2 Heterogeneous Neuromorphic Chip With Fullerene-like Interconnection Topology for Edge-AI Computing

TL;DR

This paper tackles the challenge of designing energy-efficient, flexible edge-AI hardware by integrating a heterogeneous neuromorphic processor with a RISC-V CPU on a 55 nm SoC. It introduces core innovations including a ZSPE/SPE-based neuromorphic core with spike sparsity, partial membrane potential updates, and non-uniform weight quantization, plus a fullerene-like NoC with multi-mode CMRouters and tight CPU coupling via an extended neuromorphic unit. The resulting chip demonstrates a record energy efficiency of $0.96$ pJ/SOP on NMNIST, a neuron density of $30.23$ K/mm$^2$, and a power density of $0.52$ mW/mm$^2$ on a $5.42$ mm$^2$ die in $55$ nm, while consuming $2.8$–$113$ mW. These results show strong potential for scalable, decentralized on-chip edge-AI computing with significant power and area advantages over prior work.

Abstract

Edge-AI computing requires high energy efficiency, low power consumption, and relatively high flexibility and compact area, challenging the AI-chip design. This work presents a 0.96 pJ/SOP heterogeneous neuromorphic system-on-chip (SoC) with fullerene-like interconnection topology for edge-AI computing. The neuromorphic core integrates different technologies to augment computing energy efficiency, including sparse computing, partial membrane potential updates, and non-uniform weight quantization. Multiple neuromorphic cores and multi-mode routers form a fullerene-like network-on-chip (NoC). The average degree of communication nodes exceeds traditional topologies by 32%, with a minimal degree variance of 0.93, allowing advanced decentralized on-chip communication. Additionally, the NoC can be scaled up through extended off-chip high-level router nodes. A RISC-V CPU and a neuromorphic processor are tightly coupled and fabricated within a 5.42 mm^2 die area under 55 nm CMOS technology. The chip has a low power density of 0.52 mW/mm^2, reducing 67.5% compared to related works, and achieves a high neuron density of 30.23 K/mm^2. Eventually, the chip is demonstrated to be effective on different datasets and achieves 0.96 pJ/SOP energy efficiency.

Figures (8)

• Figure 1: Scheme of the neuromorphic core.
• Figure 2: Computing process of ZSPE and SPE.
• Figure 3: Measurement of a neuromorphic core.
• Figure 4: Scheme of the fullerene-like NoC and CMRouter.
• Figure 5: Measurement of the NoC and the CMRouter.