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Reconfigurable FPGA-Based Solvers For Sparse Satellite Control

Anis Hamadouche, Yun Wu, Mathini Sellathurai, Andrew M. Wallace, Joao F. C. Mota

TL;DR

The paper tackles energy-efficient, real-time satellite orientation control in Non-Terrestrial Networks by implementing a reconfigurable FPGA-based solver for a sparsity-promoting MPC. It develops a first-order operator-splitting approach (WLM-ADMM) and derives Moreau envelope gradient descent updates suitable for hardware implementation, enabling a tunable balance between precision and power via bit-width adjustments. A rigorous FPGA-in-the-loop validation on a ZCU106 demonstrates how fixed-point and floating-point representations impact both control performance and power consumption, revealing trade-offs such as stability versus reduced power when lowering bit-width or supply voltage. The work highlights the practical viability of power-aware, sparse MPC on FPGA for autonomous, energy-constrained satellite control and outlines future work on nonlinear MPC implementations.

Abstract

This paper introduces a novel reconfigurable and power-efficient FPGA (Field-Programmable Gate Array) implementation of an operator splitting algorithm for Non-Terrestial Network's (NTN) relay satellites model predictive orientation control (MPC). Our approach ensures system stability and introduces an innovative reconfigurable bit-width FPGA-based optimization solver. To demonstrate its efficacy, we employ a real FPGA-In-the-Loop hardware setup to control simulated satellite dynamics. Furthermore, we conduct an in-depth comparative analysis, examining various fixed-point configurations to evaluate the combined system's closed-loop performance and power efficiency, providing a holistic understanding of the proposed implementation's advantages.

Reconfigurable FPGA-Based Solvers For Sparse Satellite Control

TL;DR

The paper tackles energy-efficient, real-time satellite orientation control in Non-Terrestrial Networks by implementing a reconfigurable FPGA-based solver for a sparsity-promoting MPC. It develops a first-order operator-splitting approach (WLM-ADMM) and derives Moreau envelope gradient descent updates suitable for hardware implementation, enabling a tunable balance between precision and power via bit-width adjustments. A rigorous FPGA-in-the-loop validation on a ZCU106 demonstrates how fixed-point and floating-point representations impact both control performance and power consumption, revealing trade-offs such as stability versus reduced power when lowering bit-width or supply voltage. The work highlights the practical viability of power-aware, sparse MPC on FPGA for autonomous, energy-constrained satellite control and outlines future work on nonlinear MPC implementations.

Abstract

This paper introduces a novel reconfigurable and power-efficient FPGA (Field-Programmable Gate Array) implementation of an operator splitting algorithm for Non-Terrestial Network's (NTN) relay satellites model predictive orientation control (MPC). Our approach ensures system stability and introduces an innovative reconfigurable bit-width FPGA-based optimization solver. To demonstrate its efficacy, we employ a real FPGA-In-the-Loop hardware setup to control simulated satellite dynamics. Furthermore, we conduct an in-depth comparative analysis, examining various fixed-point configurations to evaluate the combined system's closed-loop performance and power efficiency, providing a holistic understanding of the proposed implementation's advantages.
Paper Structure (5 sections, 26 equations, 7 figures)

This paper contains 5 sections, 26 equations, 7 figures.

Table of Contents

  1. INTRODUCTION
  2. PROBLEM FORMULATION
  3. MAIN RESULTS
  4. EXPERIMENTAL RESULTS
  5. CONCLUSION

Figures (7)

  • Figure 1: FPGA-In-the-Loop simulation of MPC with control horizon of $10$ samples, $64$ bit-width and $380$ mW of average power.
  • Figure 2: FPGA-In-the-Loop simulation of MPC with control horizon of $10$ samples, $28$ bit-width and $293$ mW of average power
  • Figure 3: FPGA-In-the-Loop simulation of MPC with control horizon of $10$ samples, $W = 34$ bit-width, PL voltage of $0.85$ V and $298$ mW of average power.
  • Figure 4: Real-time measurements of power, voltage, and current for 32 bits floating-point configuration.
  • Figure 5: Simulated dynamics and control signals of FPGA-In-the-Loop MPC with 34 bits fixed-point configuration.
  • ...and 2 more figures