Chiplets on Wheels: Review Paper on Holistic Chiplet Solutions for Autonomous Vehicles

TL;DR

The paper argues that chiplet-based holistic silicon solutions are essential to meet the automotive industry’s rising compute demands in a post-Moore’s-law era. It presents a throughput-oriented ADAS/infotainment micro-architecture, a methodology for evaluating chiplet architectures, and gem5-based architectural simulations, complemented by thermally-aware packaging with microfluidic cooling. Through qualitative and quantitative assessments, it demonstrates that chiplets can reduce cost by about 4×, deliver roughly 4.5× higher performance, and offer competitive power profiles compared with monolithic SoCs, while enabling flexible IP integration across automotive domains. The work also surveys interconnect ecosystems (UCIe, BoW, AIB, etc.), analyzes security and reliability under ISO 21434, and investigates packaging options (NuLink, 2.5D RDL interposers, and Apple UltraFusion) to support scalable, memory-rich, chiplet-based automotive platforms. Collectively, these findings support chiplet adoption as a practical, scalable path to software-defined, high-assurance automotive compute with robust thermal management.

Abstract

On the advent of the slow death of Moore's law, the silicon industry is moving towards a new era of chiplets. The automotive industry is experiencing a profound transformation towards software-defined vehicles, fueled by the surging demand for automotive compute chips, expected to reach 20-22 billion by 2030. High-performance compute (HPC) chips become instrumental in meeting the soaring demand for computational power. Various strategies, including centralized electrical and electronic architecture and the innovative Chiplet Systems, are under exploration. The latter, breaking down System-on-Chips (SoCs) into functional units, offers unparalleled customization and integration possibilities. The research accentuates the crucial open Chiplet ecosystem, fostering collaboration and enhancing supply chain resilience. In this paper, we address the unique challenges that arise when attempting to leverage chiplet-based architecture to design a holistic silicon solution for the automotive industry. We propose a throughput-oriented micro-architecture for ADAS and infotainment systems alongside a novel methodology to evaluate chiplet architectures. Further, we develop in-house simulation tools leveraging the gem5 framework to simulate latency and throughput. Finally, we perform an extensive design of thermally-aware chiplet placement and develop a micro-fluids-based cooling design.

Figures (36)

• Figure 1: A High-Level E&E Architecture : The chart above provides a high-level schematic representation of the input, output, and task categories within E&E architectures
• Figure 2: Block Diagram for BoW Architecture
• Figure 3: BoW Trace Length And Data Rate
• Figure 4: BoW Speeds
• Figure 5: Ring-based interconnect architecture