Non-intrusive data-driven model order reduction for circuits based on Hammerstein architectures

TL;DR

The paper tackles the computational burden of transistor-level circuit simulations by proposing a non-intrusive model order reduction approach based on a Hammerstein architecture, learned via system identification. It separates static nonlinear behavior from linear dynamics using a sequential training procedure: a table-based DC I–V nonlinearity φ is identified first, followed by learning a linear state-space block (A,B,C,D) that shapes φ’s output into transient currents, yielding a compact, accurate reduced-order surrogate. Demonstrations on a CMOS differential amplifier and a 51-transistor operational amplifier show that with internal state dimension n ≤ 3, the Hammerstein ROM reproduces both DC and transient responses across a wide operating range and frequencies up to several GHz, often outperforming fully intrusively derived models in speed and data efficiency. The results indicate strong potential for fast, non-intrusive circuit-level analysis and rapid design iteration, especially for “scripted” circuit blocks like op-amps and comparators.

Abstract

We demonstrate that system identification techniques can provide a basis for effective, non-intrusive model order reduction (MOR) for common circuits that are key building blocks in microelectronics. Our approach is motivated by the practical operation of these circuits and utilizes a canonical Hammerstein architecture. To demonstrate the approach we develop parsimonious Hammerstein models for a nonlinear CMOS differential amplifier and an operational amplifier circuit. We train these models on a combination of direct current (DC) and transient Spice circuit simulation data using a novel sequential strategy to identify their static nonlinear and linear dynamical parts. Simulation results show that the Hammerstein model is an effective surrogate for for these types of circuits that accurately and efficiently reproduces their behavior over a wide range of operating points and input frequencies.

Figures (18)

• Figure 1: Schematic of the CMOS nonlinear differential amplifier circuit considered in this work Prasad_16_report. The body of each NMOS transistor is connected to ground, and the body of each PMOS transistor is connected to $V_{\text{DD}}$.
• Figure 2: A basic linear differential amplifier model. The impedances $Z_{\text{in}}$ and $Z_{\text{out}}$ may in general comprise both resistive and reactive parts. The supply voltages $+V$ and $-V$ establish upper and lower bounds on the voltage produced by the dependent source.
• Figure 3: Block diagram of the generic Hammerstein model structure, where $\varphi$ is a memoryless nonlinear function, $H$ is a linear time-invariant system, $u$ is the input, and $y$ is the output.
• Figure 4: Block diagram of the proposed Hammerstein model for the CMOS DiffAmp circuit. The left dashed-outline section depicts the nonlinearity $\varphi$ as described in Section \ref{['ssec:nonlinearity_design']}; the right dashed-outline section depicts a general linear time-invariant system.
• Figure 5: Q3 interpolant surfaces for DC output current $I^h_3$ as a function of input voltages $(V_1,V_2)$ with fixed output voltage $V_3$.