Improving the Fidelity of CNOT Circuits on NISQ Hardware

TL;DR

This work tackles the fidelity limitations of CNOT circuits on NISQ devices by introducing a cost function that tightly tracks the average gate fidelity, enabling noise-aware routing via the NAPermRowCol algorithm. The method leverages parity-matrix representations and Steiner-tree guided reductions to route CNOTs under nearest-neighbor constraints while factoring in gate-error rates, and it deliberately avoids ancillary qubits to maximize efficiency. Empirical benchmarks on IBM fake backends show that Cost accurately approximates the error probability and that NAPermRowCol substantially reduces the synthesized CNOT count and improves fidelity compared to noise-agnostic methods and Qiskit, with up to 9x fidelity improvements and significant gate-count reductions. The results demonstrate scalable, hardware-aware compilation for NISQ-era quantum circuits and point to extensions to broader circuit routing under realistic noise models.

Abstract

We introduce an improved CNOT synthesis algorithm that considers nearest-neighbour interactions and CNOT gate error rates in noisy intermediate-scale quantum (NISQ) hardware. Compared to IBM's Qiskit compiler, it improves the fidelity of a synthesized CNOT circuit by about 2 times on average (up to 9 times). It lowers the synthesized CNOT count by a factor of 13 on average (up to a factor of 162). Our contribution is twofold. First, we define a $\textsf{Cost}$ function by approximating the average gate fidelity $F_{avg}$. According to the simulation results, $\textsf{Cost}$ fits the error probability of a noisy CNOT circuit, $\textsf{Prob} = 1 - F_{avg}$, much tighter than the commonly used cost functions. On IBM's fake Nairobi backend, it matches $\textsf{Prob}$ to within $10^{-3}$. On other backends, it fits $\textsf{Prob}$ to within $10^{-1}$. $\textsf{Cost}$ accurately quantifies the dynamic error characteristics and shows remarkable scalability. Second, we propose a noise-aware CNOT routing algorithm, NAPermRowCol, by adapting the leading Steiner-tree-based connectivity-aware CNOT synthesis algorithms. A weighted edge is used to encode a CNOT gate error rate and $\textsf{Cost}$-instructed heuristics are applied to each reduction step. NAPermRowCol does not use ancillary qubits and is not restricted to certain initial qubit maps. Compared with algorithms that are noise-agnostic, it improves the fidelity of a synthesized CNOT circuit across varied NISQ hardware. Depending on the benchmark circuit and the IBM backend selected, it lowers the synthesized CNOT count up to $56.95\%$ compared to ROWCOL and up to $21.62\%$ compared to PermRowCol. It reduces the synthesis $\textsf{Cost}$ up to $25.71\%$ compared to ROWCOL and up to $9.12\%$ compared to PermRowCol. Our method can be extended to route a more general quantum circuit, giving a powerful new tool for compiling on NISQ devices.

Figures (33)

• Figure 1: The action of a CNOT gate corresponds to a column (row) operation on $I$. This allows us to derive the parity matrix of a CNOT circuit.
• Figure 2: A $4$-qubit CNOT circuit C is uniquely represented by a $4 \times 4$ parity matrix A. Row $i$ denotes the state on the input qubit wire $i$. Column $j$ is the parity term $\textbf{b}_j$ on the output qubit wire $j'$. The bipartite graph interpretation of C shows the information propagation in the CNOT circuit. Different ways of colouring edges help us interpret a row and column in A.
• Figure 3: The parity matrix of an $n$-qubit SWAP circuit is an $n \times n$ permutation matrix.
• Figure 4: Solutions to a Steiner tree problem Steiner(G,S) are not unique. (a) $G$ is a 12-vertex grid with $S = \{2,3,7,11\}$. The terminal nodes are coloured in red. (b) $T_0$ is a solution to Steiner(G,S). The edges of the Steiner tree $T_0$ are coloured in green. Its Steiner nodes are the intermediary nodes in the Steiner tree, $V_{T_0}\setminus S=\{1,4,10\}$. (c) $T_1$ is an alternative solution to Steiner(G, S). Its set of Steiner nodes is $V_{T_1}\setminus S=\{4,5,8\}$.
• Figure 5: Visualize the initial qubit map on a hardware topology.

Theorems & Definitions (76)

• Definition 1.1
• Remark 1.1
• Definition 1.2
• Definition 1.3
• Example 1.1
• Example 1.2
• Definition 1.4
• Lemma 1.1
• proof
• Lemma 1.2