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Wavefront Threading Enables Effective High-Level Synthesis

Blake Pelton, Adam Sapek, Ken Eguro, Daniel Lo, Alessandro Forin, Matt Humphrey, Jinwen Xi, David Cox, Rajas Karandikar, Johannes de Fine Licht, Evgeny Babin, Adrian Caulfield, Doug Burger

TL;DR

The paper tackles the difficulty of writing hardware in a productive high-level language without sacrificing RTL-quality performance. It introduces Kanagawa and its Wavefront Threading execution model, enabling explicit fine-grained concurrency with a memory model designed for efficient hardware mapping. Through comprehensive examples, compiler mappings, and extensive ASIC/FPGA benchmarks, the authors show that Kanagawa can yield production-quality hardware with competitive latency, area, and throughput while significantly reducing code size. The work highlights Kanagawa’s potential to streamline hardware design, support iterative architecture exploration, and serve as a platform well-suited for generative AI-assisted hardware development.

Abstract

Digital systems are growing in importance and computing hardware is growing more heterogeneous. Hardware design, however, remains laborious and expensive, in part due to the limitations of conventional hardware description languages (HDLs) like VHDL and Verilog. A longstanding research goal has been programming hardware like software, with high-level languages that can generate efficient hardware designs. This paper describes Kanagawa, a language that takes a new approach to combine the programmer productivity benefits of traditional High-Level Synthesis (HLS) approaches with the expressibility and hardware efficiency of Register-Transfer Level (RTL) design. The language's concise syntax, matched with a hardware design-friendly execution model, permits a relatively simple toolchain to map high-level code into efficient hardware implementations.

Wavefront Threading Enables Effective High-Level Synthesis

TL;DR

The paper tackles the difficulty of writing hardware in a productive high-level language without sacrificing RTL-quality performance. It introduces Kanagawa and its Wavefront Threading execution model, enabling explicit fine-grained concurrency with a memory model designed for efficient hardware mapping. Through comprehensive examples, compiler mappings, and extensive ASIC/FPGA benchmarks, the authors show that Kanagawa can yield production-quality hardware with competitive latency, area, and throughput while significantly reducing code size. The work highlights Kanagawa’s potential to streamline hardware design, support iterative architecture exploration, and serve as a platform well-suited for generative AI-assisted hardware development.

Abstract

Digital systems are growing in importance and computing hardware is growing more heterogeneous. Hardware design, however, remains laborious and expensive, in part due to the limitations of conventional hardware description languages (HDLs) like VHDL and Verilog. A longstanding research goal has been programming hardware like software, with high-level languages that can generate efficient hardware designs. This paper describes Kanagawa, a language that takes a new approach to combine the programmer productivity benefits of traditional High-Level Synthesis (HLS) approaches with the expressibility and hardware efficiency of Register-Transfer Level (RTL) design. The language's concise syntax, matched with a hardware design-friendly execution model, permits a relatively simple toolchain to map high-level code into efficient hardware implementations.
Paper Structure (47 sections, 15 figures, 1 table)

This paper contains 47 sections, 15 figures, 1 table.

Table of Contents

  1. Introduction
  2. Motivational Example
  3. Kanagawa Language
  4. Wavefront Threading
  5. Shared State
  6. Wavefront Consistency
  7. Scheduling Constraints and Synchronization
  8. Thread Ordering with Control Flow
  9. Function Calls
  10. Asynchronous Functions
  11. Batched Functions
  12. Loops
  13. Conditionals
  14. Parallelism
  15. Functions
  16. ...and 32 more sections

Figures (15)

  • Figure 1: CountIf Histogram in C.
  • Figure 4: Ordering example code and execution. Each column represents a step of the global clock. Each of the first four rows corresponds to a different static memory access. Values of thread local variables are shown in curly braces. The next two rows show the values of the shared variables. Threads may arbitrarily stall but must maintain their relative ordering. This is shown by the stall of threads $T1$ and $T2$ at time 2.
  • Figure 6: Statically scheduled CountIf Histogram.
  • Figure 7: Dynamically scheduled CountIf Histogram.
  • Figure 8: Replicated CountIf Histogram.
  • ...and 10 more figures