Multi-qubit Lattice Surgery Scheduling

TL;DR

This work tackles scheduling of multi-qubit lattice-surgery operations in two-dimensional surface-code architectures by formulating the problem as the LSSP, with inputs being a Pauli-rotation circuit and a hardware layout. It introduces a two-tier approach: (i) a primary packing problem that selects packs of mutually independent rotations to cover the circuit, and (ii) a packing subproblem that constructs feasible ancilla-patch Steiner trees to realize those rotations with minimal bus-qubit usage, all under an earliest-available-first scheduling policy. A scalable greedy algorithm combines dependency-graph construction (favoring a trivial commutation rule for large circuits) with forest packing to place Steiner trees, enabling parallel execution of non-conflicting operations. Extensive experiments on random and application-inspired circuits show large reductions in circuit length and execution-time potential after transpilation, with the transpilation delivering about an 89% reduction in circuit length and an 84% reduction in the expected number of logical cycles, thereby supporting scalable resource estimation for fault-tolerant quantum computation. The study also highlights trade-offs between parallelism and gate-count reduction and suggests directions for further improvements, including alternative codes and layouts such as color codes. All mathematical notation in the text uses $...$ delimiters where applicable.

Abstract

Fault-tolerant quantum computation using two-dimensional topological quantum error correcting codes can benefit from multi-qubit long-range operations. By using simple commutation rules, a quantum circuit can be transpiled into a sequence of solely non-Clifford multi-qubit gates. Prior work on fault-tolerant compilation avoids optimal scheduling of such gates since they reduce the parallelizability of the circuit. We observe that the reduced parallelization potential is outweighed by the significant reduction in the number of gates. We therefore devise a method for scheduling multi-qubit lattice surgery using an earliest-available-first policy, solving the associated forest packing problem using a representation of the multi-qubit gates as Steiner trees. Our extensive testing on random and application-inspired circuits demonstrates the method's scalability and performance. We show that the transpilation significantly reduces the circuit length on the set of circuits tested, and that the resulting circuit of multi-qubit gates has a further reduction in the expected circuit execution time compared to serial execution.

Figures (7)

• Figure 1: Rules for converting Clifford + $T$ gates into Pauli product rotations. The letters within the boxes on the right ($X$, $Z$) represent the Pauli matrix, while the box colour represents the rotation angle, either $\pi/4$ (purple) or $\pi/8$ (green).
• Figure 2: Three types of surface code patches within a 3 $\times$ 2 grid of tiles. The edges of the patches represent the Pauli operators $X$ (dashed) and $Z$ (solid). Shown are example (a) single-tile single-qubit, (b) two-tile single-qubit, and (c) two-tile two-qubit patches. Single-qubit patches follow an $XZXZ$ pattern initialized in any position desired, such as (a) and (b). Patches can be extended to multiple tiles using lattice surgery.
• Figure 3: Example of two parallel multi-qubit measurements performed using lattice surgery in a surface code grid with data qubits (shown in purple), bus qubits (green), a magic state storage qubit (red), and an ancillary qubit (pink). The $\pi/4$ rotation corresponds to an $X \otimes I \otimes I \otimes Z$ rotation connected to the ancillary qubit available using eight bus qubits, and the $\pi/8$ rotation corresponds to an $I \otimes Y \otimes Y \otimes I$ rotation connected to the magic state storage qubit available using five bus qubits.
• Figure 4: Examples of central zones comprising data qubits surrounded by bus qubits, and with ancillary and magic state storage qubits located at the boundary of the central zone. Given a layout of type (a) with $A$ aisles of data qubits and $P$ data qubit patches in each aisle, a modification can be done to transform it into a layout of type (b) by adding $P(2A+1)$ extra bus qubit tiles. Layout (b) facilitates the parallelization of multi-qubit measurements, as qubits can be connected using multiple paths.
• Figure 5: Example layout for (a) the logical resources in the central zone converted to (b) an adjacency graph. Qubit patches and their accessible Pauli operators are converted into vertices in the adjacency graph, and edges represent the adjacencies between patches. The operators $Z_iZ_j$ (top) and $X_iX_j$ (bottom) of the two-tile, two-qubit patches can be represented by their own vertices, but additional constraints would be required to be added to our models to account for the choice of vertices to use when there is a possibility of connecting the ancilla patch to these operators. We therefore disregard these operators to simplify the generation of the ancilla patches.