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Cryogenic Characterization of Low-Frequency Noise in 40-nm CMOS

Gerd Kiene, Sadik Ilik, Luigi Mastrodomenico, Masoud Babaie, Fabio Sebastiano

TL;DR

Problem: understanding LFN behavior in CMOS at cryogenic temperatures is essential for cryo-electronic systems but poorly characterized. Approach: large-scale, statistically robust LFN measurements on a 40-nm bulk-CMOS chip across many geometries, biases, and two temperatures, including a focused study of a systematic cryogenic Lorentzian. Findings: cryogenic LFN includes a systematic Lorentzian overlay not seen at room temperature; area scaling persists, with NMOS bias dependence largely temperature-invariant and PMOS showing noise reductions. Significance: results improve predictive noise models and guide design practices for cryogenic analog circuits (e.g., PLLs, TIAs) and quantum hardware, while highlighting the need to account for Lorentzian noise in cryogenic design.

Abstract

This paper presents an extensive characterization of the low-frequency noise (LFN) at room temperature (RT) and cryogenic temperature (4.2 K) of 40-nm bulk-CMOS transistors. The noise is measured over a wide range of bias conditions and geometries to generate a comprehensive overview of LFN in this technology. While the RT results are in-line with the literature and the foundry models, the cryogenic behavior diverges in many aspects. These deviations include changes with respect to RT in magnitude and bias dependence that are conditional on transistor type and geometry, and even an additional systematic Lorentzian feature that is common among individual devices. Furthermore, we find the scaling of the average LFN with the area and its variability to be similar between RT and 4.2 K, with the cryogenic scaling reported systematically for the first time. The findings suggest that, as no consistent decrease of LFN at lower temperatures is observed while the white noise is reduced, the impact of LFN for precision analog design at cryogenic temperatures gains a more predominant role.

Cryogenic Characterization of Low-Frequency Noise in 40-nm CMOS

TL;DR

Problem: understanding LFN behavior in CMOS at cryogenic temperatures is essential for cryo-electronic systems but poorly characterized. Approach: large-scale, statistically robust LFN measurements on a 40-nm bulk-CMOS chip across many geometries, biases, and two temperatures, including a focused study of a systematic cryogenic Lorentzian. Findings: cryogenic LFN includes a systematic Lorentzian overlay not seen at room temperature; area scaling persists, with NMOS bias dependence largely temperature-invariant and PMOS showing noise reductions. Significance: results improve predictive noise models and guide design practices for cryogenic analog circuits (e.g., PLLs, TIAs) and quantum hardware, while highlighting the need to account for Lorentzian noise in cryogenic design.

Abstract

This paper presents an extensive characterization of the low-frequency noise (LFN) at room temperature (RT) and cryogenic temperature (4.2 K) of 40-nm bulk-CMOS transistors. The noise is measured over a wide range of bias conditions and geometries to generate a comprehensive overview of LFN in this technology. While the RT results are in-line with the literature and the foundry models, the cryogenic behavior diverges in many aspects. These deviations include changes with respect to RT in magnitude and bias dependence that are conditional on transistor type and geometry, and even an additional systematic Lorentzian feature that is common among individual devices. Furthermore, we find the scaling of the average LFN with the area and its variability to be similar between RT and 4.2 K, with the cryogenic scaling reported systematically for the first time. The findings suggest that, as no consistent decrease of LFN at lower temperatures is observed while the white noise is reduced, the impact of LFN for precision analog design at cryogenic temperatures gains a more predominant role.
Paper Structure (8 sections, 3 equations, 8 figures, 1 table)

This paper contains 8 sections, 3 equations, 8 figures, 1 table.

Table of Contents

  1. Introduction
  2. Methods
  3. Characterization results
  4. Systematic Lorentzian
  5. Bias dependence
  6. Area dependence
  7. Discussion
  8. Conclusion

Figures (8)

  • Figure 1: a) Micrograph of the test chip; b) Schematic of each NMOS; c) Schematic of each PMOS. The thick-oxide selection transistors are shown with a thicker-gate symbol.
  • Figure 2: Example N/PMOS (1×1) DC-characteristics at Vds=50mV: a) drain current Id, b) transconductance gm, c) output resistance ro.
  • Figure 3: Noise spectra for NMOS (a, c) and PMOS (b, d) with W$\times$L =1×1 at Vgs=1.1V and Vds=1.1V (a,b) and Vds=50mV (c,d), respectively. 8 devices at the same bias points are shown.
  • Figure 4: Mean noise spectra for PMOS and NMOS devices with W×L=1µm×1µm and W×L=1µm×40nm with Vgs=Vds for logarithmically spaced overdrive-voltage (Vod=Vgs-Vth) at RT (a-d) and 4.2K (e-h). Each curve represents the mean of 8 individual devices. The RT plots also show the corresponding simulations of the foundry model with dashed lines.
  • Figure 5: Mean noise spectra at 4.2K. The output (a, c) and input-referred (b, d) of eight N/PMOS devices with WxL=4µmx4µm are shown, to demonstrate the bias dependence of the systematic Lorentzian.
  • ...and 3 more figures