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Fast ML-driven Analog Circuit Layout using Reinforcement Learning and Steiner Trees

Davide Basso, Luca Bortolussi, Mirjana Videnovic-Misic, Husni Habal

TL;DR

The paper addresses the bottleneck in analog IC layout by framing floorplanning as a Markov Decision Process and combining reinforcement learning with Steiner-tree-based routing. It introduces two RL-based floorplanning approaches (RL-SA and Pure RL) along with an Obstacle Avoiding Rectilinear Steiner Tree (OARSMT) global router, all integrated into a procedural ANAGEN-based pipeline. The method is evaluated on an OTA circuit, showing dramatic improvements such as template-generation time dropping from $16$ hours to $57.48$ seconds and a $13.8\%$ reduction in layout area, with runtimes approaching $1.5\%$ of manual effort. Overall, the work demonstrates a viable path to automated, verifiable analog layouts that can substantially shorten design cycles and improve consistency in layout quality.

Abstract

This paper presents an artificial intelligence driven methodology to reduce the bottleneck often encountered in the analog ICs layout phase. We frame the floorplanning problem as a Markov Decision Process and leverage reinforcement learning for automatic placement generation under established topological constraints. Consequently, we introduce Steiner tree-based methods for the global routing step and generate guiding paths to be used to connect every circuit block. Finally, by integrating these solutions into a procedural generation framework, we present a unified pipeline that bridges the divide between circuit design and verification steps. Experimental results demonstrate the efficacy in generating complete layouts, eventually reducing runtimes to 1.5% compared to manual efforts.

Fast ML-driven Analog Circuit Layout using Reinforcement Learning and Steiner Trees

TL;DR

The paper addresses the bottleneck in analog IC layout by framing floorplanning as a Markov Decision Process and combining reinforcement learning with Steiner-tree-based routing. It introduces two RL-based floorplanning approaches (RL-SA and Pure RL) along with an Obstacle Avoiding Rectilinear Steiner Tree (OARSMT) global router, all integrated into a procedural ANAGEN-based pipeline. The method is evaluated on an OTA circuit, showing dramatic improvements such as template-generation time dropping from hours to seconds and a reduction in layout area, with runtimes approaching of manual effort. Overall, the work demonstrates a viable path to automated, verifiable analog layouts that can substantially shorten design cycles and improve consistency in layout quality.

Abstract

This paper presents an artificial intelligence driven methodology to reduce the bottleneck often encountered in the analog ICs layout phase. We frame the floorplanning problem as a Markov Decision Process and leverage reinforcement learning for automatic placement generation under established topological constraints. Consequently, we introduce Steiner tree-based methods for the global routing step and generate guiding paths to be used to connect every circuit block. Finally, by integrating these solutions into a procedural generation framework, we present a unified pipeline that bridges the divide between circuit design and verification steps. Experimental results demonstrate the efficacy in generating complete layouts, eventually reducing runtimes to 1.5% compared to manual efforts.
Paper Structure (14 sections, 2 equations, 3 figures, 3 tables)

This paper contains 14 sections, 2 equations, 3 figures, 3 tables.

Table of Contents

  1. Introduction
  2. Problem Definition
  3. Floorplanning
  4. Routing
  5. Automatic Layout Generation
  6. Topological Representation of a Circuit Floorplan
  7. Simulated Annealing and Reinforcement Learning
  8. Structures Recognition and Device Shapes Generation
  9. RL-SA Floorplanning
  10. Pure RL Floorplanning
  11. RL Training Setup
  12. Post-processing & Routing
  13. Experimental Results and Discussion
  14. Conclusions

Figures (3)

  • Figure 1: High-level schematic of the AI-powered automated layout pipeline with this paper contributions highlighted in green.
  • Figure 2: OTA schematic (a), corresponding floorplan and global routing configuration (b) and its rendering with ANAGEN tracklines (c).
  • Figure 3: OTA layout generated from our automatic pipeline (a) and manually from a physical design engineer (b) using ANAGEN layout generator.