Evaluating Vulnerability of Chiplet-Based Systems to Contactless Probing Techniques

TL;DR

The paper investigates the vulnerability of chiplet-based systems to contactless probing, focusing on inter-chiplet interposer wires. It demonstrates laser probing against a chiplet-based FPGA fabricated in $16$nm and packaged on a $65$nm interposer, and compares the exposure of interposer drivers with on-die wires while evaluating delay-based sensors. The results show probe-induced delay changes of about $0.792$ ps at full laser power ($100\%$), which are difficult to distinguish from environmental drift, underscoring a vulnerability in chiplet interfaces. It proposes masking the data with a TRNG-based one-time-pad as a mitigation and discusses the need for robust, in-situ delay sensing to reliably detect probing. Collectively, the work highlights a practical security risk in chiplet architectures and motivates development of stronger defenses for inter-chiplet communication.

Abstract

Driven by a need for ever increasing chip performance and inclusion of innovative features, a growing number of semiconductor companies are opting for all-inclusive System-on-Chip (SoC) architectures. Although Moore's Law has been able to keep up with the demand for more complex logic, manufacturing large dies still poses a challenge. Increasingly the solution adopted to minimize the impact of silicon defects on manufacturing yield has been to split a design into multiple smaller dies called chiplets which are then brought together on a silicon interposer. Advanced 2.5D and 3D packaging techniques that enable this kind of integration also promise increased power efficiency and opportunities for heterogeneous integration. However, despite their advantages, chiplets are not without issues. Apart from manufacturing challenges that come with new packaging techniques, disaggregating a design into multiple logically and physically separate dies introduces new threats, including the possibility of tampering with and probing exposed data lines. In this paper we evaluate the exposure of chiplets to probing by applying laser contactless probing techniques to a chiplet-based AMD/Xilinx VU9P FPGA. First, we identify and map interposer wire drivers and show that probing them is easier compared to probing internal nodes. Lastly, we demonstrate that delay-based sensors, which can be used to protect against physical probes, are insufficient to protect against laser probing as the delay change due to laser probing is only 0.792ps even at 100\% laser power.

Figures (13)

• Figure 1: Diagram illustrating the basic working principles of EOP and EOFM, as described in Sections \ref{['subsec:eop']} and \ref{['subsec:eofm']} respectively. Apart from EOFM involving scanning the beam, the two techniques differ in how the reflected light is processed.
• Figure 2: (a) Diagram of chiplet-to-chiplet connections through interposer, and (b) corresponding photograph of delidded AMD/Xilinx chiplet-based VU9P FPGA used in evaluation. The red arrows in each picture annotate the chiplet boundaries.
• Figure 3: Illustration of the setup used for data collection.
• Figure 4: Photon emission highlights circuits with high switching activity, such as groups of custom placed ring oscillators in (a), which are used as guideposts to locate circuits of interests like a Laguna column in (b). A single Laguna tile is outlined in green. The red arrows annotate the boundary between two chiplets.
• Figure 5: EOFM of 32 fabric flip-flops and 24 Laguna registers toggling at 100MHz under 20x magnification. The spot pointed to by the yellow arrow represents a group of two registers.