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Fully parallel implementation of digital memcomputing on FPGA

Dyk Chung Nguyen, Yuriy V. Pershin

TL;DR

The paper addresses solving hard 3-SAT instances by encoding Boolean variables as continuous memcomputing dynamics and implementing these dynamics in hardware on an FPGA. It presents a fully parallel forward-Euler solver using integer arithmetic, achieving a fixed step time of 96 ns and enabling simultaneous updates of hundreds of ODEs. Compared with a sequential C++ baseline, it reports a roughly three-order-of-magnitude speedup and a polynomial reduction in time-to-solution with problem size, up to around 150 variables on the tested FPGA; the observed scaling exponents are $a=2.32\pm0.04$ for the C++ steps and $b=3.36\pm0.04$ for real-time solution. The work demonstrates the feasibility and potential of FPGA-based memcomputing for compact yet challenging optimization problems and discusses pathways to scale with larger devices.

Abstract

We present a fully parallel digital memcomputing solver implemented on a field-programmable gate array (FPGA) board. For this purpose, we have designed an FPGA code that solves the ordinary differential equations associated with digital memcomputing in parallel. A feature of the code is the use of only integer-type variables and integer constants to enhance optimization. Consequently, each integration step in our solver is executed in 96~ns. This method was utilized for difficult instances of the Boolean satisfiability (SAT) problem close to a phase transition, involving up to about 150 variables. Our results demonstrate that the parallel implementation reduces the scaling exponent by about 1 compared to a sequential C++ code on a standard computer. Additionally, compared to C++ code, we observed a time-to-solution advantage of about three orders of magnitude. Given the limitations of FPGA resources, the current implementation of digital memcomputing will be especially useful for solving compact but challenging problems.

Fully parallel implementation of digital memcomputing on FPGA

TL;DR

The paper addresses solving hard 3-SAT instances by encoding Boolean variables as continuous memcomputing dynamics and implementing these dynamics in hardware on an FPGA. It presents a fully parallel forward-Euler solver using integer arithmetic, achieving a fixed step time of 96 ns and enabling simultaneous updates of hundreds of ODEs. Compared with a sequential C++ baseline, it reports a roughly three-order-of-magnitude speedup and a polynomial reduction in time-to-solution with problem size, up to around 150 variables on the tested FPGA; the observed scaling exponents are for the C++ steps and for real-time solution. The work demonstrates the feasibility and potential of FPGA-based memcomputing for compact yet challenging optimization problems and discusses pathways to scale with larger devices.

Abstract

We present a fully parallel digital memcomputing solver implemented on a field-programmable gate array (FPGA) board. For this purpose, we have designed an FPGA code that solves the ordinary differential equations associated with digital memcomputing in parallel. A feature of the code is the use of only integer-type variables and integer constants to enhance optimization. Consequently, each integration step in our solver is executed in 96~ns. This method was utilized for difficult instances of the Boolean satisfiability (SAT) problem close to a phase transition, involving up to about 150 variables. Our results demonstrate that the parallel implementation reduces the scaling exponent by about 1 compared to a sequential C++ code on a standard computer. Additionally, compared to C++ code, we observed a time-to-solution advantage of about three orders of magnitude. Given the limitations of FPGA resources, the current implementation of digital memcomputing will be especially useful for solving compact but challenging problems.
Paper Structure (8 sections, 3 equations, 3 figures)

This paper contains 8 sections, 3 equations, 3 figures.

Table of Contents

  1. Introduction
  2. memcomputing equations for 3-SAT
  3. Methods
  4. Generation of SAT instances
  5. FPGA implementation
  6. C++ code
  7. Results
  8. Discussion and conclusion

Figures (3)

  • Figure 1: Vivado simulations of the fully parallel solution of Barthel $M/N=4.3$ instances on FPGA. (a) Steps to solution on FPGA (shown for ten instances of each selected problem size) and median number of steps to solution found using the C++ code. (b) Time to solution on FPGA (this work), small-size FPGA (from chung23), and C++ code.
  • Figure 2: Experimental data showing the relationship between the time to solution and number of integration steps for various $M/N=4.3$ problems. The relationship is evidently linear.
  • Figure 3: Utilization of LUTs depending on the problem size. The dashed horizontal line denotes the maximum number of LUTs in our VCU118 evaluation board. The fitting curve is $-204557+9559\cdot N$.