On Hardware-efficient Inference in Probabilistic Circuits

TL;DR

The paper tackles hardware-efficient inference for probabilistic circuits (PCs) deployed on edge devices by introducing Addition As Int ($AAI$) to approximate multiplications, enabling a low-cost, largely linear computation via an $exp$-$sum$-$log$ scheme. It develops theoretical error analyses for MAR and MAP queries, and adds a safe multiplier replacement and an error-correction mechanism to control accuracy loss. The authors provide a hardware-oriented architecture and an empirical evaluation showing substantial energy reductions, up to $649\times$ for MAP and $357\times$ for MAR, while maintaining robust accuracy. Overall, this work demonstrates that probabilistic circuits can be efficiently accelerated in hardware with controlled approximation, enabling practical embedded probabilistic reasoning on edge devices.

Abstract

Probabilistic circuits (PCs) offer a promising avenue to perform embedded reasoning under uncertainty. They support efficient and exact computation of various probabilistic inference tasks by design. Hence, hardware-efficient computation of PCs is highly interesting for edge computing applications. As computations in PCs are based on arithmetic with probability values, they are typically performed in the log domain to avoid underflow. Unfortunately, performing the log operation on hardware is costly. Hence, prior work has focused on computations in the linear domain, resulting in high resolution and energy requirements. This work proposes the first dedicated approximate computing framework for PCs that allows for low-resolution logarithm computations. We leverage Addition As Int, resulting in linear PC computation with simple hardware elements. Further, we provide a theoretical approximation error analysis and present an error compensation mechanism. Empirically, our method obtains up to 357x and 649x energy reduction on custom hardware for evidence and MAP queries respectively with little or no computational error.

Figures (9)

• Figure 1: Potential hardware cost savings (\ref{['fig:l:aai']}) for inference in probabilistic circuits through approximate computing with addition-as-int (AAI).
• Figure 2: Illustration of a PC (a) over discrete RVs ($\textcolor{colour4}{X_1}, \textcolor{colour2}{X_2}, \textcolor{colour3}{X_3}$) and the corresponding hardware realization of MAP inference (b). For this, sum nodes are replaced by max operators, and an additional propagation path for information bits ($v_i$) is added to back-track the most probable path. Arrows indicate propagation direction.
• Figure 3: Input dependent approximation error introduced through Mitchell's method.
• Figure 4: MAP accuracy (ACC) and MAR error for AAI (dashed) and exact (solid) multipliers for varying numbers of mantissa bits and four different numbers of exponent bits ( 8 bits, 9 bits, 10 bits, 11 bits ). All results are computed relative to exact multiplication with 64-bit. AAI significantly reduces the energy costs (x-axis) while obtaining comparable and robust results compared to exact multipliers in most cases.
• Figure 5: Power consumption of multipliers on $65$nm CMOS using $8$ exponent bits for increasing number of mantissa bits.

Theorems & Definitions (3)

• Definition 2.1: Smooth & Decomposability
• Definition 2.2: Determinism
• Definition B.1: Induced tree zhao2016collapsed