Inferring Message Flows From System Communication Traces

TL;DR

This work tackles the challenge of deriving accurate message flow specifications from complex SoC traces to aid validation, debugging, and design understanding. It introduces a causality-graph-based mining pipeline, an acceptance-ratio metric $AR$ for evaluation, and the novel concept of essential causalities to boost accuracy and speed. The method comprises causality-graph construction, pruning, base-model selection, evaluation, and iterative refinement, with optimization techniques like essential causality extraction and EMF to handle realistic traces such as those from GEM5. Empirical results on synthetic and GEM5 traces show significant improvements in accuracy over prior approaches and demonstrate practical utility for verification, debugging, and security monitoring, while acknowledging the need for some user-guided decisions and future work on runtime optimization and deep-learning-assisted path identification.

Abstract

This paper proposes a novel method for automatically inferring message flow specifications from the communication traces of a system-on-chip (SoC) design that captures messages exchanged among the components during a system execution. The inferred message flows characterize the communication and coordination of components in a system design for realizing various system functions, and they are essential for SoC validation and debugging. The proposed method relieves the burden of manual development and maintenance of such specifications on human designers. Our method also uses a new accuracy metric, \emph{acceptance ratio}, to evaluate the quality of the mined specifications instead of the specification size often used in the previous work, enabling more accurate specifications to be mined. Furthermore, this paper introduces the concept of essential causalities to enhance the accuracy of the message flow mining and accelerate the mining process. The effectiveness of the proposed method is evaluated on both synthetic traces and traces generated from executing several system models in GEM5. In both cases, the proposed method achieves superior accuracies compared to a previous approach. Additionally, this paper includes some practical use cases.

Figures (6)

• Figure 1: (a) A simplified SoC architecture example, (b) Message sequence diagram for the CPU downstream read flows. This diagram is parameterized with $x$ being $0$ or $1$. Only communications involving CPU, Cache, and Mem blocks are included for a clear illustration.
• Figure 2: (a) Graph representation of CPU downstream flows given in Fig. \ref{['fig:soc-ex']}(b) where the nodes are labeled with messages as defined given (b). (c) gives the flows' initial and terminal messages.
• Figure 3: Causality graph from trace (\ref{['eq:ex-trace']}): (a) nodes and edges with support information, (b) edges marked with forward/backward confidences, (c) pruned version of the graph.
• Figure 4: (a) GEM5 Full-System (FS) design. (b) GEM5 System Emulation (SE) design. : Communication Monitor
• Figure 5: (a) A flow mined from the GEM5 threads trace. (b) GEM5 documentation's memory write miss sequence. (c) Two flows mined from the GEM5 threads trace depicting a clean eviction scenario, not in GEM5 documentation.

Theorems & Definitions (5)

• Definition 3.1
• Definition 4.1
• Definition 4.2
• Definition 4.3
• Definition 4.4